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[13:35:24] <solrize> IvanSB, i think you should post on olimex forum. this channel is very very quiet.
[13:36:21] <malina> slightly quieter than a fart in a funeral
[13:38:22] <IvanSB> solrize, your response was quicker than I'd expect. Not a bad starting
[13:38:35] <plaes> IvanSB: if you're talking about the SPI where the boot flash is connected (SPI0), then it's these pins: https://github.com/linux-sunxi/sunxi-tools/blob/master/fel-spiflash.c#L218
[13:43:04] <IvanSB> plaes, not the one connected to the flash. I can see 2 in /dev/ spidev1.0 and spidev2.0. Any of the 2. I'd like to know if by default the CS signal is controlled by hardware or I should pick up a GPIO to raise/lower it by software
[13:44:36] <IvanSB> mmm it seems something got truncated
[13:45:12] <IvanSB> plaes, not the one connected to flash. I can see 2 in /dev any of them.
[13:45:40] <IvanSB> I'd like to know if by default the CS signal is controlled by hardware or I should pick up a GPIO to raise/lower it by software
[13:46:39] <plaes> yeah, this is the question to the forum
[13:47:37] <plaes> I've been using self-rolled images myself where only spi0 is enabled
[13:50:29] <IvanSB> plaes, Olimex Debian image seems good enough for me... I'd just like to avoid some hours of trial and error since there are many alternatives for SPI pin assignment. Going to find the best forum to ask. Thx
[13:52:00] <plaes> would be helpful if you mention the version
[13:53:00] <IvanSB> plaes, kernel? 5.10.36-olimex
[20:02:13] <Tsvetan> IvanSB this file may help https://github.com/OLIMEX/OLINUXINO/blob/master/DOCUMENTS/OLIMAGE/Olimage-guide.pdf
IRC #olimex 2021-06-16
[13:32:29] <IvanSB> hi, is there some place where I can find what are the pins assigned to SPI in the default image of LIME2? thanks[13:35:24] <solrize> IvanSB, i think you should post on olimex forum. this channel is very very quiet.
[13:36:21] <malina> slightly quieter than a fart in a funeral
[13:38:22] <IvanSB> solrize, your response was quicker than I'd expect. Not a bad starting
[13:38:35] <plaes> IvanSB: if you're talking about the SPI where the boot flash is connected (SPI0), then it's these pins: https://github.com/linux-sunxi/sunxi-tools/blob/master/fel-spiflash.c#L218
[13:43:04] <IvanSB> plaes, not the one connected to the flash. I can see 2 in /dev/ spidev1.0 and spidev2.0. Any of the 2. I'd like to know if by default the CS signal is controlled by hardware or I should pick up a GPIO to raise/lower it by software
[13:44:36] <IvanSB> mmm it seems something got truncated
[13:45:12] <IvanSB> plaes, not the one connected to flash. I can see 2 in /dev any of them.
[13:45:40] <IvanSB> I'd like to know if by default the CS signal is controlled by hardware or I should pick up a GPIO to raise/lower it by software
[13:46:39] <plaes> yeah, this is the question to the forum
[13:47:37] <plaes> I've been using self-rolled images myself where only spi0 is enabled
[13:50:29] <IvanSB> plaes, Olimex Debian image seems good enough for me... I'd just like to avoid some hours of trial and error since there are many alternatives for SPI pin assignment. Going to find the best forum to ask. Thx
[13:52:00] <plaes> would be helpful if you mention the version
[13:53:00] <IvanSB> plaes, kernel? 5.10.36-olimex
[20:02:13] <Tsvetan> IvanSB this file may help https://github.com/OLIMEX/OLINUXINO/blob/master/DOCUMENTS/OLIMAGE/Olimage-guide.pdf
