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[01:36:10] <braunr> i know this is summer vacation, and i can wait :)
[01:36:29] <braunr> is there a way to get jtag access to an a64-olinuxino board somehow ?
[01:36:53] <braunr> if not, is there any plan to make a 64-bits multicore cortex based board with a jtag interface in the future ?
[10:40:45] <leon-anavi> hi
[12:26:34] <nedko> the ATX12V 5VSB line doesnt work well so far. The HDD module attached on SATA port of a lime2 screams quite bad. i think about bypassing/decoupling/filtering as possible improvement :)
IRC #olimex 2017-07-31
[01:35:58] <braunr> hello[01:36:10] <braunr> i know this is summer vacation, and i can wait :)
[01:36:29] <braunr> is there a way to get jtag access to an a64-olinuxino board somehow ?
[01:36:53] <braunr> if not, is there any plan to make a 64-bits multicore cortex based board with a jtag interface in the future ?
[10:40:45] <leon-anavi> hi
[12:26:34] <nedko> the ATX12V 5VSB line doesnt work well so far. The HDD module attached on SATA port of a lime2 screams quite bad. i think about bypassing/decoupling/filtering as possible improvement :)
