August 09, 2022, 05:55:05 pm

Recent posts

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21
MSP430 / Re: MOD EKG waveform
Last post by LubOlimex - July 20, 2022, 12:57:19 pm
What USB-UART adapter do you use? Did you follow all advice from "Connecting MOD-EKG to PC via MOD-USB-RS232 board.pdf"? Did you select the proper COM port (how is the USB-UART adapter listed)?
22
MSP430 / MOD EKG waveform
Last post by daekhan - July 20, 2022, 09:20:58 am
Hi.
I buy MOD EKG Board.
And I tested and connect between mod-ekg and PC, run scope.exe.
HeartRate count value is displayed LCD.

But, GUI waveform is strange form. not PQRST form.

The ECG waveform picture in olimex application doc, is diffenent my GUI.

Why??

Cloud you check this?

Thanks.
23
New Product Ideas / Future-proof idea for TERES
Last post by gDanix - July 20, 2022, 12:48:55 am
Short version:

Why don't design a new main board for the TERES laptop that, instead of having a SOC or a CPU, has a programmable FPGA. This way the "hardware" could be easily "upgradeable", just like Olimex iCE40HX8K board?

----------------------------
Long version:

There's a lot of threads asking or proposing improvements to the current version (TERES-PCB1-A64) of the main board of the TERES DIY Laptop, which is natural, since this laptop was engineered to be upgradeable and repairable.

Nonetheless the A64 chip is behaving apparently well, Olimex has lots of expertise developing boards with this SOC, and actually it doesn't seem to be the need to upgrade this board. Instead, I want to spark debate around an idea that is in my head, in the hope that it's useful somehow for Olimex guys: Replacing the main computing unit (SOC or CPU) by a FPGA.

This has some advantages:
  • The computing unit can be customized: You can set your CPU to be RISCV, or to have 8-bits floating point extensions, or vectors, or don't want any of these, and instead more, simpler cores for faster operation?
  • It can also be upgradeable: Hardware bugs are costly, Olimex could easily roll out changes in the hardware description to make the device more efficient, robust or whatnot

But I see myself a lot of hard challenges to overcome:
  • The FPGA IC has to be powerful enough to compete with current A64, at least, while maintains a decent level of openness
  • Probably, a completely new board must be designed, not just an upgrade of the SOC chip of the current design
  • there's a lot of interfaces to standardize (how the FPGA should talk to peripherals. Will it include the main memory?. And the flash memory?)
  • Relying on third-party designs while Olimex kickstart their own optimized versions would create endless compatibility problems, so this would not be anything close to end-user ready at launch
  • Olimex would probably have to adapt or engineer a complete new core for every architecture they wish to support (But don't really know the state of custom cores out there. Maybe there are already customizable designs that can be used as an starting point for this project), along with the software

At the end of the day, a huge sum of costs...

I've found Olimex's responses to threads where people ask for RISCV versions of TERES quite revealing: I didn't know that there were so many openness problems with current RISCV chips (I'm a software person, sorry!), so I'm really excited to hear what's your opinion on this (and, believe me, don't worry if it's negative, don't try to sweeten it. I would like to hear a truthful, professional opinion).

Thanks! And sorry for the long post.
Dani.
24
UEXT / Re: MOD-IO programming with no...
Last post by JohnS - July 19, 2022, 01:17:36 pm
Possibly the doc at
https://www.kernel.org/doc/html/latest/spi/spidev.html
will help.

It mentions SPI_IOC_WR_MODE32 and SPI_IOC_RD_MODE32 etc.

Some systems don't support SPI_NO_CS but whether the Linux version & board you're using does or not I don't know - hunt around to see.

Generally SPI uses a CS so...

Obviously (I think), without CS you can only have one SPI device and I suppose must hardwire its CS appropriately.

I'm a bit puzzled why avrdude does that? (If it does.)

John
25
UEXT / Re: MOD-IO programming with no...
Last post by JerkoNikolic - July 19, 2022, 12:08:38 pm
Yeah, the SPI worked from the start (tested with the 2,8" LCD).
The issue is specifically when avrdude tries to set the SPI mode to SPI_NO_CS
ioctl(fd_spidev, SPI_IOC_WR_MODE32, SPI_NO_CS)
26
UEXT / Re: MOD-IO programming with no...
Last post by LubOlimex - July 19, 2022, 11:58:46 am
I meant that it works in general, we haven't used it with avrdude for programming, but with other boards that use SPI. In newer Olimage images different SPIs can be enabled or disabled via script "olinuxino-overlay".
27
UEXT / Re: MOD-IO programming with no...
Last post by JerkoNikolic - July 18, 2022, 05:28:40 pm
The image used is A20-OLinuXino-buster-base-202103
I'm not sure I understand you regarding SPI. Do you mean that the SPI works in general or specifically with avrdude?
SPI works for us as well in normal use cases, the trouble is specifically with avrdude.
Have you had cases where you used UEXT ports to program other boards?
28
ST / Re: can you please give me pin...
Last post by LubOlimex - July 18, 2022, 09:33:24 am
The link to the image was empty, can you try again or explain with words what exactly do you mean.
29
ST / Re: can you please give me pin...
Last post by anotherbrick - July 15, 2022, 04:40:17 pm
thank you
30
ESP32 / Re: ESP32-POE-ISO randomly fre...
Last post by LubOlimex - July 15, 2022, 03:07:36 pm
I have no idea but you might test and compare with some other mqqt software, like what was published at the bottom here:

https://github.com/OLIMEX/ESP32-POE/issues/6
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