October 30, 2026, 04:33:30 PM

Recent posts

#1
ESP32 / Re: Ethernet link not connecti...
Last post by LubOlimex - Today at 02:18:05 PM
Are you 100% sure you have ESP32-POE-ISO-Wrover-EA? Can you see what is written on the module itself? It should be "ESP32-WROVER-EA".

I reproduced your initialization approach on an ESP32-POE-ISO-WROVER using ESP-IDF 5.5.5. It links immediately and remains stable, so the code and newer ESP-IDF do not appear to be the general cause.

Please test with my code: https://ftp.olimex.com/TEMP/wrover-esp-idf/ (there is README.md inside the archive with more details). If the problem remains try a short known-good LAN cable, another switch port, and preferably another network and computer, then compare the PHY registers and 50 MHz RMII clock. Let me know how it goes.
#2
ESP32 / Re: Ethernet link not connecti...
Last post by Edac145 - Today at 11:53:21 AM
Quote from: LubOlimex on Today at 11:40:33 AMDid you check the user's manual?

Which pin do you use for the Ethernet clock? Is it GPIO0?

MDC – 23
MDIO – 18
PHY reset – 12
PHY RMII clock – 0 (0 is for boards with WROVER module)



yes i am using pin 0 for clock
#define ETH_PHY_ADDR        0
#define ETH_MDC_GPIO        23
#define ETH_MDIO_GPIO       18
#define ETH_PHY_PWR_GPIO    12
#define ETH_RMII_CLK_GPIO   0     /* WROVER: 0, WROOM: 17 */                                     

i am pasting my ethernet init code below,
* ---------------- Ethernet init ---------------- */
static void ethernet_init(void)
{
    /* TCP/IP stack + default event loop */
    ESP_ERROR_CHECK(esp_netif_init());
    ESP_ERROR_CHECK(esp_event_loop_create_default());

    esp_netif_config_t netif_cfg = ESP_NETIF_DEFAULT_ETH();
    s_eth_netif = esp_netif_new(&netif_cfg);

    const esp_timer_create_args_t timer_args = {
        .callback = fallback_timer_cb,
        .name = "dhcp_fallback",
    };
    ESP_ERROR_CHECK(esp_timer_create(&timer_args, &s_fallback_timer));

    /* MAC (internal EMAC, RMII) */
    eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG();
    eth_esp32_emac_config_t emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG();
    emac_config.interface = EMAC_DATA_INTERFACE_RMII;
    emac_config.smi_gpio.mdc_num  = ETH_MDC_GPIO;
    emac_config.smi_gpio.mdio_num = ETH_MDIO_GPIO;
    /* ESP32 generates the 50 MHz RMII reference clock for the LAN8720A */
    emac_config.clock_config.rmii.clock_mode = EMAC_CLK_OUT;
    emac_config.clock_config.rmii.clock_gpio = ETH_RMII_CLK_GPIO;
    esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&emac_config, &mac_config);

    /* PHY (LAN8720A). GPIO12 powers/resets the PHY: it stays low (PHY off) until the
     * MAC has started the RMII clock, as required by the LAN8720A. */
    eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG();
    phy_config.phy_addr       = ETH_PHY_ADDR;
    phy_config.reset_gpio_num = ETH_PHY_PWR_GPIO;
    esp_eth_phy_t *phy = esp_eth_phy_new_lan87xx(&phy_config);

    /* Driver install + attach to TCP/IP */
    esp_eth_config_t eth_config = ETH_DEFAULT_CONFIG(mac, phy);
    esp_eth_handle_t eth_handle = NULL;
    ESP_ERROR_CHECK(esp_eth_driver_install(&eth_config, &eth_handle));
    s_eth_handle = eth_handle;
    ESP_ERROR_CHECK(esp_netif_attach(s_eth_netif, esp_eth_new_netif_glue(eth_handle)));

    ESP_ERROR_CHECK(esp_event_handler_register(ETH_EVENT, ESP_EVENT_ANY_ID, &eth_event_handler, NULL));
    ESP_ERROR_CHECK(esp_event_handler_register(IP_EVENT, IP_EVENT_ETH_GOT_IP, &got_ip_event_handler, NULL));

    vTaskDelay(pdMS_TO_TICKS(100));

    printf("Clock GPIO=%d\n", emac_config.clock_config.rmii.clock_gpio);
    printf("Clock mode=%d\n", emac_config.clock_config.rmii.clock_mode);
    printf("Interface=%d\n", emac_config.interface);

    ESP_ERROR_CHECK(esp_eth_start(eth_handle));
    xTaskCreate(phy_diag_task, "phy_diag", 3072, NULL, 3, NULL);
}

void app_main(void)
{
    esp_err_t ret = nvs_flash_init();
    if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) {
        ESP_ERROR_CHECK(nvs_flash_erase());
        ret = nvs_flash_init();
    }
    ESP_ERROR_CHECK(ret);

    ethernet_init();
    start_webserver();   /* lwIP accepts connections as soon as the interface has an IP */
}
#3
ESP32 / Re: Ethernet link not connecti...
Last post by LubOlimex - Today at 11:40:33 AM
Did you check the user's manual?

Which pin do you use for the Ethernet clock? Is it GPIO0?

MDC – 23
MDIO – 18
PHY reset – 12
PHY RMII clock – 0 (0 is for boards with WROVER module)
#4
ESP32 / Ethernet link not connecting -...
Last post by Edac145 - Today at 08:47:35 AM
My Olimex ESP32-POE-ISO-WROVER-EA, hardware revision N1, does not establish an Ethernet link with either my laptop or router. The same cable works between the laptop and router. The board's power LED is on, but its LINK and ACT1 LEDs remain off. ESP32 logs show the LAN8710 PHY responds over MDIO (ID 0007:C0F1), but link stays down (link=0, auto-negotiation incomplete). I also tried with ethernet basic example. it is also not working. I am giving power through mico usb port. Could you advise whether this indicates a board hardware fault and how to proceed?                    i have pasted my log file below                                                              --- 0x40080400: _invalid_pc_placeholder at E:/Program_Files/EspTools/Espressif/frameworks/.espressif/v6.0.2/esp-idf/components/xtensa/xtensa_vectors.S:2259
entry 0x40080644
--- 0x40080644: call_start_cpu0 at E:/Program_Files/EspTools/Espressif/frameworks/.espressif/v6.0.2/esp-idf/components/bootloader/subproject/main/bootloader_start.c:27
I (27) boot: ESP-IDF v6.0.2 2nd stage bootloader
I (27) boot: compile time Oct 29 2026 15:47:41
I (28) boot: Multicore bootloader
I (29) boot: chip revision: v3.0
I (32) boot.esp32: SPI Speed      : 40MHz
I (35) boot.esp32: SPI Mode      : DIO
I (39) boot.esp32: SPI Flash Size : 4MB
I (42) boot: Enabling RNG early entropy source...
I (47) boot: Partition Table:
I (49) boot: ## Label            Usage          Type ST Offset  Length
I (56) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (62) boot:  1 phy_init        RF data          01 01 0000f000 00001000
I (69) boot:  2 factory          factory app      00 00 00010000 00100000
I (75) boot: End of partition table
I (79) esp_image: segment 0: paddr=00010020 vaddr=3f400020 size=14c14h ( 85012) map
I (116) esp_image: segment 1: paddr=00024c3c vaddr=3ffb0000 size=02cb4h ( 11444) load
I (121) esp_image: segment 2: paddr=000278f8 vaddr=40080000 size=08720h ( 34592) load
I (136) esp_image: segment 3: paddr=00030020 vaddr=400d0020 size=3c9b4h (248244) map
I (224) esp_image: segment 4: paddr=0006c9dc vaddr=40088720 size=03d08h ( 15624) load
I (231) esp_image: segment 5: paddr=000706ec vaddr=50000000 size=00028h (    40) load
I (238) boot: Loaded app from partition at offset 0x10000
I (238) boot: Disabling RNG early entropy source...
I (250) cpu_start: Multicore app
I (258) cpu_start: GPIO 3 and 1 are used as console UART I/O pins
I (258) cpu_start: Pro cpu start user code
I (259) cpu_start: cpu freq: 160000000 Hz
I (260) app_init: Application information:
I (264) app_init: Project name:    01_uart_test
I (269) app_init: App version:      uart-v0.1.0-dirty
I (273) app_init: Compile time:    Oct 29 2026 15:46:55
I (278) app_init: ELF file SHA256:  760071bc4...
I (283) app_init: ESP-IDF:          v6.0.2
I (286) efuse_init: Min chip rev:    v0.0
I (290) efuse_init: Max chip rev:    v3.99
I (294) efuse_init: Chip rev:        v3.0
I (298) heap_init: Initializing. RAM available for dynamic allocation:
I (305) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (310) heap_init: At 3FFB4188 len 0002BE78 (175 KiB): DRAM
I (315) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (320) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (326) heap_init: At 4008C428 len 00013BD8 (78 KiB): IRAM
I (332) spi_flash: detected chip: generic
I (335) spi_flash: flash io: dio
I (339) main_task: Started on CPU0
I (339) main_task: Calling app_main()
I (399) esp_eth.netif.netif_glue: 7c:9e:bd:dc:5f:f3
I (399) esp_eth.netif.netif_glue: ethernet attached to netif
Clock GPIO=0
Clock mode=1
Interface=0
I (4499) eth_test: Ethernet started
I (4499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (4499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
I (4499) eth_test: Web server started on port 80
I (4509) main_task: Returned from app_main()
I (7499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (7499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
I (10499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (10499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
I (13499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (13499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
I (16499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (16499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
I (19499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (19499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
I (22499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (22499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
I (25499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (25499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
I (28499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (28499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
I (31499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (31499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
I (34499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (34499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
I (37499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (37499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
I (40499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (40499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
I (43499) eth_test: PHY ID1=0x0007 ID2=0xc0f1 BMSR=0x7809 (link=0) R31=0x0040
I (43499) eth_test: PHY R0=0x3000 R5=0x0001 R17=0x0002 (energy=1) R18=0x60e0
#5
Neo6502 / Re: Prophet server for the Neo...
Last post by Ralf - October 29, 2026, 05:38:37 PM
Hi Béné,

thanks for your reply.
I'm using Trinity v0.16.69 and NeoDOS v0.32.1

That was the Olimex UART MOD-WIFI-ESP8266 I used.
On first boot with Trinity, I got a flood of endless error messages. These messages were somehow turned into files, so I got a lot of filenames like ER and ROR and so on. They were mostly 0 bytes, so I didn't bother to open and read any of them, and the system is working nicely and stable with the Pi Pico, so I don't feel compelled to replicate that event. ;-)
However, as the MOD-WIFI-ESP8266 is the only peripheral I haven't plugged into the Neo6502 again, I strongly suspect it was the culprit.

As for the keymaps, yes, NeoBasic does support German, however, I don't want to boot Trinity, run NeoBasic for the German Keymap, and then run NeoDOS again because of its advantages.
Sure, I guess a few lines in AUTOEXEC.BAT and autostart.bas will do the trick, but it's still not a neat solution.
Anyways. In NeoBasic with German keymap, the ö ä ü ß give the English (US?) mapping, i.e. ; ' [ -

Lastly, did you do something to speed up the whole Neo6502? There is this clockspeed.bas demo and it gives me a clockspeed of around 6.8MHz, and the test.bas demo which generates a Mandelbrot set also runs faster than it used to.
Which is cool though. :-)

So long
Cheers
#6
A20 / Re: Wich board to correctly mo...
Last post by LubOlimex - October 29, 2026, 01:53:29 PM
The output shows that the system is already running from SATA (/dev/sda1 is /). olinuxino-sd-to-sata excludes the current root device, so "Failed to detect SATA device" is expected in this state. Reflash the complete Olimage image to the whole SD card, first boot it with SATA disconnected, and verify findmnt -no SOURCE / reports /dev/mmcblk0p1. Then reconnect SATA, verify SD is still root, and rerun the migration script. If it again boots SATA, please provide the UART boot log, especially the "U-boot loaded from" and "Boot script loaded from" lines - these are at beginning of boot and require USB-serial cable.
#7
Neo6502 / Re: Prophet server for the Neo...
Last post by béné - October 29, 2026, 02:00:24 AM
Thanks a lot for the kind words, and for testing Trinity so thoroughly!

- Olimex UART WiFi card: you are right, it is not supported. Only the USB CDC modem (Pico W, "picowifiusb", on the USB-A port) is handled. I honestly don't know what wrote those stray files to your USB drive, and nothing about this card is documented yet. To dig into it, could you tell me: your Trinity version, the exact names of the stray files, the text of the error messages, and how the card is connected (UART or USB)? I can't promise a fix or a warning yet, but I'll note it in the docs.

- Keymaps: the firmware already embeds several locales (fm, gb, sw, us, fr, de, fi, it, ch), so a German one is there, inherited from upstream (Olav Schettler's code). You can already select it from NeoBASIC with LOCALE "de" (or through the API, group 1, function 6). There is no NeoDOS command, no persistent setting and no selection at boot yet, so it has to be set again at each launch. I'll look into adding a NeoDOS command and a remembered setting, with no date for now. I have only validated the French keymap (AZERTY) on real hardware; the German one is untested on my side, so please tell me what you get with LOCALE "de" (ä ö ü ß in particular).

Thanks again for the feedback,
Béné
#8
A20 / Re: Wich board to correctly mo...
Last post by oly - October 28, 2026, 01:45:19 PM
Hello,

Sorry, for the delay.

root@TOTO:~# olinuxino-sd-to-sata

Detecting board...

Detecting the root device...
Root partition:         /dev/sda1
Root device:            /dev/sda

Detecting SATA device...
Failed to detect SATA device!

root@TOTO:~# lsblk
NAME        MAJ:MIN RM   SIZE RO TYPE MOUNTPOINTS
sda           8:0    0 111,8G  0 disk
└─sda1        8:1    0 111,8G  0 part /
mmcblk0     179:0    0  14,8G  0 disk
└─mmcblk0p1 179:1    0   1,1G  0 part

root@TOTO:~# df .
Sys. de fichiers blocs de 1K Utilisé Disponible Uti% Monté sur
/dev/sda1          114784676 1262712  107645052   2% /
#9
ESP32 / Re: ESP32-POE (ISO) LiPo Batte...
Last post by LubOlimex - October 28, 2026, 08:13:43 AM
Removing FET2 won't work in your case. You need to carefully unsolder and remove U3 TP4054 (the battery charger IC). Refer to the schematic. It is SOT23-5 package, chip with 5 pins.
#10
ESP32 / Re: ESP32-POE (ISO) LiPo Batte...
Last post by oguzhan306 - October 27, 2026, 08:16:33 PM
Hi LubOlimex,

I have a similar question, but my use case is slightly different.

I'm using an ESP32-POE-ISO Rev. M in a device that will operate in cold environments, potentially below 0°C.

The device is normally powered via PoE, and I want to use a Li-ion battery strictly as a backup power source in case PoE fails.

I do not want the battery to be charged by the board under any circumstances, particularly because charging Li-ion batteries at sub-zero temperatures can be unsafe.

My requirements are:

When PoE is available, the device should operate from PoE.

When PoE is lost, the battery should automatically take over.

When PoE returns, the device should switch back to PoE.

The battery must never be charged by the board.

A brief power interruption or ESP32 reset during switching is acceptable.

In your earlier reply, you mentioned removing FET2 to disable the charging circuit.

Would removing FET2 on the ESP32-POE-ISO Rev. M completely disable battery charging while preserving the automatic battery backup functionality?

If not, is there another component that could be removed or a simple hardware modification you would recommend?

Thank you for your help!