Recent posts

#1

FPGA / Re: Stability Issue with GateM...

Last post by charon030 - Today at 08:56:14 AM

Hi,
I did some more investigations.
With the design I sent you, core voltage drops from 1.098V to 1.097V. Not a big change, but a change.

I checked the voltage converters and can see that the Olimex board uses converters with 2A output current maximum. At 1.1V this corresponds to 2.2W. However, in the GateMate datasheet they consume already 2W with LFSR shift registers, see page 162 of DS1001. The headroom might be too small, in particular if there are peaks in power consumption. Just as a reference, on the Cologne Chips Devboard they use voltage converters with 3A.

Best regards
Matthias

#2

ESP32 / Re: ESP32-POE-ISO-EA-16MB full...

Last post by Ol!mexGoody - May 06, 2026, 05:54:37 PM

I found the 3D step component for the antenna variant, I replaced the original one with it. You can find both the export and only the component here:

https://ftp.olimex.com/TEMP/ESP32-PoE-ISO-revision-M/

Thanks! I updated the Fusion file with it.

#3

FPGA / Re: Stability Issue with GateM...

Last post by charon030 - May 06, 2026, 11:13:21 AM

Hi,
thanks for the offer. Note that I'm trying to gain experience with the GateMate ecosystem. The design I'm using is not for production or something but more a tool to get to know your board as well as the tool flow.

I can't upload the bit file here but added it to my cloud storage:

https://drive.proton.me/urls/PRH4ANX41R#DGguScyKprlV

You can load it with the "openFPGAloader -c dirtyJtag fract_controller.bit"

All you need to replicate is the following:
- a VGA monitor connected
- a PS/2 keyboard connected

The bit stream internally uses 16 pixel computation units with multipliers and adders.
The design achieves timing closure with 50 MHz target clock (54 MHz timing with "typical" timing setting). Utilization is still moderate:
Info:                  CPE_LT:   22480/  40960    54%
Info:                  CPE_FF:    9949/  40960    24%
Info:               CPE_RAMIO:      15/  40960     0%
Info:                RAM_HALF:       0/     64     0%


What you can see is that there are actually pixels changing their colors but the picture should be really stable. This indicates already that the computations do not finish within one clock period. The reason can be that either the timing models of Cologne Chip are too optimistic in the "typical" case or that the power supply/consumption is causing issues.

What's more: When you move the screen to an area where more computations happen (more toggling in the FPGA), the screen goes black completely. This looks really like an issue with power supply. The screen area causing this is the inner of the fractal (lots of green on the screen). To interact with the fractal, use the keyboard (cursor keys, or F1/F2 to zoom or space for automatic zoom).

If I reapeat the same test with a different parameterization (8 or 12 pixel computation units => less utilization of the FPGA), I neither see the wobbling pixels nor the screen going black.

If you need anything else, let me know.

Thanks a lot
Matthias

#4

ESP32 / Re: ESP32-POE-ISO-EA-16MB full...

Last post by LubOlimex - May 06, 2026, 10:39:40 AM

I found the 3D step component for the antenna variant, I replaced the original one with it. You can find both the export and only the component here:

https://ftp.olimex.com/TEMP/ESP32-PoE-ISO-revision-M/

#5

FPGA / Re: Stability Issue with GateM...

Last post by LubOlimex - May 06, 2026, 08:50:50 AM

Can you think of a way we can replicate it here? Can you give us a project or a file to load and steps to replicate the hang?

We are not very proficient with FPGA and FPGA software development, so if you can provide us with step by step guide to replicate it we are willing to test and perform hardware changes to see if the behavior improves with bigger capacitors and the same software as you.

#6

A64 / Re: Debian GNU/Linux 13 (Trixi...

Last post by Roman - May 05, 2026, 11:02:44 PM

Here is the devicetree overlay which I am currently using in order to fix the Ethernet download issue. I am using it together with sun50i-a64-olinuxino-emmc.dtb devicetree on Guix System originating from the mainline Linux. It should work on Debian too. If you try the overlay, please share how it goes and which revision of the board you use. Choose one of the two devicetrees which Debian ships depending on whether your board has eMMC or not.

Code Select Expand

/dts-v1/;
/plugin/;

/ {
    compatible = "allwinner,sun50i-a64";

    fragment@0 {
        target-path = "/soc/ethernet@1c30000";
        __overlay__ {
            allwinner,rx-delay-ps = <200>;
        };
    };
};
You can build it with dtc.

Code Select Expand

$ dtc -@ -I dts -O dtb -o sun50i-a64-rx-delay.dtbo sun50i-a64-rx-delay.dts
You should put it somewhere where the bootloader can find it, possibly in /boot, and configure the bootloader to apply it.

#7

ESP32 / Re: ESP32-POE-ISO-EA-16MB full...

Last post by Ol!mexGoody - May 05, 2026, 05:48:17 PM

I am not sure if I understand the first request. Do you want me to export the hardware revision M board, it is pretty much the same and the ESP32e module has the same size just a provision for the u.FL connector.

Yes, the revision M board (less important) with the U.FL connector instead of the PCB antenna (more important)

We don't have a 3D model for the antenna, we purchase it and the manufacturer didn't share one. But these are pretty generic antennas I am sure there should be one available somewhere online.

OK, thanks.

#8

FPGA / Re: Stability Issue with GateM...

Last post by charon030 - May 05, 2026, 12:43:29 PM

Hi Lub,

Thanks for your prompt response.

Actually, I'm running the board in speed mode already and I measured 1.098V.

The only thing I'm guilty of is running timing analysis in typical mode instead of worst mode. Otherwise I don't achieve timing closure, running the design at 50 MHz.

Still, the CologneChip board uses capacitors with much higher capacitance, not only for the core voltage but also for the IP banks and SERDES.

Best regards

#9

FPGA / Re: Stability Issue with GateM...

Last post by LubOlimex - May 05, 2026, 08:45:23 AM

Hello,

Can you check how is the VDD_CORE_SET1 jumper set? Is it as per default in position 2-1? Position 2-1 is "economy mode" and sets the voltage of the VDD core to 1.0V. This jumper is the rightmost at the bottom, just next to the UEXT1 connector.

Try to change it to position 3-2 (e.g. move it to the left two pins). This is "speed mode" and raises the voltage of the VDD core to 1.1V. Then test again.

Let me know if that fixes the issue.

Best regards,
Lub/OLIMEX

#10

FPGA / Stability Issue with GateMateA...

Last post by charon030 - May 05, 2026, 12:01:13 AM

Hi,

My FPGA design becomes unstable when I fill the FPGA like 50% with a compute intensive design and have varying loads.

I was wondering whether the power supply could cause this an checked the schematic. I found that the capacitors on the VDD pins are much smaller than what CologneChip is using in their Evaluation board. For instance, Olimex uses plenty of 1nF capacitors which seems very optimistic from my point of view.
The chain of capacitors being 2.2uF, 100nF, multiple 1nF.
In contrast the CologneChip board:
2.2uF, 470nF, 2x 100nF, 2x 10nF.

Could this be causing the issues I'm seeing?

I didn't use the SERDES yet, but also for the VDD_SER, the difference in dimensioning the capacitors is huge.

Thanks