Future-proof idea for TERES

Started by gDanix, July 20, 2022, 12:48:55 AM

Previous topic - Next topic


Short version:

Why don't design a new main board for the TERES laptop that, instead of having a SOC or a CPU, has a programmable FPGA. This way the "hardware" could be easily "upgradeable", just like Olimex iCE40HX8K board?

Long version:

There's a lot of threads asking or proposing improvements to the current version (TERES-PCB1-A64) of the main board of the TERES DIY Laptop, which is natural, since this laptop was engineered to be upgradeable and repairable.

Nonetheless the A64 chip is behaving apparently well, Olimex has lots of expertise developing boards with this SOC, and actually it doesn't seem to be the need to upgrade this board. Instead, I want to spark debate around an idea that is in my head, in the hope that it's useful somehow for Olimex guys: Replacing the main computing unit (SOC or CPU) by a FPGA.

This has some advantages:
  • The computing unit can be customized: You can set your CPU to be RISCV, or to have 8-bits floating point extensions, or vectors, or don't want any of these, and instead more, simpler cores for faster operation?
  • It can also be upgradeable: Hardware bugs are costly, Olimex could easily roll out changes in the hardware description to make the device more efficient, robust or whatnot

But I see myself a lot of hard challenges to overcome:
  • The FPGA IC has to be powerful enough to compete with current A64, at least, while maintains a decent level of openness
  • Probably, a completely new board must be designed, not just an upgrade of the SOC chip of the current design
  • there's a lot of interfaces to standardize (how the FPGA should talk to peripherals. Will it include the main memory?. And the flash memory?)
  • Relying on third-party designs while Olimex kickstart their own optimized versions would create endless compatibility problems, so this would not be anything close to end-user ready at launch
  • Olimex would probably have to adapt or engineer a complete new core for every architecture they wish to support (But don't really know the state of custom cores out there. Maybe there are already customizable designs that can be used as an starting point for this project), along with the software

At the end of the day, a huge sum of costs...

I've found Olimex's responses to threads where people ask for RISCV versions of TERES quite revealing: I didn't know that there were so many openness problems with current RISCV chips (I'm a software person, sorry!), so I'm really excited to hear what's your opinion on this (and, believe me, don't worry if it's negative, don't try to sweeten it. I would like to hear a truthful, professional opinion).

Thanks! And sorry for the long post.


If the CM4 was used in TERES users could choose, including choosing emerging FPGA or RISC-V options