Compiling the kernel with different system clocks

Started by marcolazzaroni, September 24, 2012, 08:11:19 pm

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I successfully built kernel 3.6 by using the step-by-steps instructions by Fadil Berisha (thank you Fadil!! :-) )
Now I need to set some parameters such as SSP's clock.
See at page 21-3.
How do I set the involved parameters in the  kernel? I have to look deep in menuconfig or in the bootlets sections?
Thank you in advance!

Fadil Berisha

You can look at bootlets but some registers are redefined when kernel take control. Base control registers are defined in header file mx23.h  So, look at header files for drivers: imx23-mmc, imx23-i2c, imx23-spi (available in linux-next). I would suggest to start with main clock driver drivers/clk/mxs/clk-imx23.c.

Fadil Berisha


Hello Fadil,
  thank you for your relay.
I've looked into clk-imx23.c.
I successfully changed the base clock and I managed to get a base speed 10 times slower (I've set ref_xtal to 240 M instead of 24M).
Anyway I can't understand the ssp_div setting made with mxs_clk_div() function.

clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29);

SSP is the address of the HW_CLK_CTRL_SSP register (see page 4-19), and it seems the right register.
So I want to increase the divider in order to slow down the SSP Clock.

This is the declaration of mxs_clk_div:

struct clk *mxs_clk_div(const char *name, const char *parent_name,
                         void __iomem *reg, u8 shift, u8 width, u8 busy)

'width' seems related to the size (in bits) of the divider, 9, so it seems correct. I suppose that busy=29 is the divider, but changing it to a greater number (in the 0..511 range - I tried 229) does not change the ssp clock speed: with an oscilloscope I always read 50 MHz on SSP clock pin.

Has anyone any sugestions?


I was able to reduce ssp clock.
/drivers/mmc/host/mxs-mmc.c needs to be modified.

See mxs_mmc_set_ios

if I change

if (ios->clock)
             mxs_mmc_set_clk_rate(host, ios->clock);


if (ios->clock)
             mxs_mmc_set_clk_rate(host, ios->clock/10);

...I get 5Mhz instead of 50MHz.

Looking for a smarter way now.

Now the next step is to enable SSP2, but this is covered by another post of mine (not solved yet).

Fadil Berisha

Hi Marco

Is not clear for me if you refer only to declaration of mxs_clk_div or function himself. Please have look at file drivers/clk/mxs/clk-div.c - there is defined function. Also  include/linux/clk-provider.h contain related documentation (flag  CLK_DIVIDER_ONE_BASED). Quote from IMX23RM.pdf, page 94 - 4.8.8 Synchronous Serial Port Clock Control Register Description  "NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0."

Fadil Berisha/koliqi


Fadil, I'm now able to change the speed.
It is done by changing the parameters of mxs_mmc_set_clk_rate() function.