July 19, 2024, 09:05:00 AM

iCE40HX8K-EVB 100 MHz oscillator

Started by ivanovp, February 28, 2024, 09:09:48 PM

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ivanovp

Hi,

I've got two iCE40HX8K-EVB boards. An older one from 2019, and a newer one from 2023. My project generates VGA output and has got a RISC-V soft processor. The older hardware produces stable VGA output, the newer one produces flickering image on a LCD monitor. I think that the 100 MHz oscillator is the root cause of the problem. I measured the two oscillator signals.
100 MHz clock on new board (peak-to-peak voltage is ~3.4V):

100 MHz clock on new board (peak-to-peak voltage is only ~1.4V!):

Older board (HXO-36A oscillator):

Newer board (CETCLJ oscillator):


Maybe the problem is not with the voltage, but jitter. Can anyone give advice where to look?
I'll try to use a different clock source or replace the CETCLJ oscillator with a different one.

Thanks and best regards,
Peter

ivanovp

#1
So I answer to myself:
After adding 16 MHz oscillator to PIO1_28 and using a PLL to generate 100 MHz internally the VGA signal is stable.
So the flickering VGA was caused by CETCLJ 100 MHz oscillator. I'll replace it.

Edit: I found another solution. If I feed the on-board 100 MHz to the PLL and generate 100 MHz, the PLL's signal is good enough to have a stable VGA signal!

`include "pll2.v"

wire CLK; // 100 MHz output from PLL
pll2 pll2_0 (.clock_in(CLK_100M), .clock_out(CLK));
// pll2.v:
/**
 * PLL configuration
 *
 * This Verilog module was generated automatically
 * using the icepll tool from the IceStorm project.
 * Use at your own risk.
 *
 * Given input frequency:       100.000 MHz
 * Requested output frequency:  100.000 MHz
 * Achieved output frequency:   100.000 MHz
 */

module pll2(
input  clock_in,
output clock_out,
output locked
);

SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000), // DIVR =  0
.DIVF(7'b0000111), // DIVF =  7
.DIVQ(3'b011), // DIVQ =  3
.FILTER_RANGE(3'b101) // FILTER_RANGE = 5
) uut (
.LOCK(locked),
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(clock_in),
.PLLOUTCORE(clock_out)
);

endmodule