July 19, 2024, 03:17:28 AM

UEXTx5 Chip Select

Started by synologic, May 24, 2023, 09:53:41 PM

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Hi all,

a nice addition to the UEXTx5 would be to have separate CS lines for each port, this way we can do multidrop SPI and select the addressee via separate CS pins.



Thanks for the suggestion but this would complicate the board. Our idea was mainly to split I2C lines, and maybe allow for one UART and one SPI extra.
Technical support and documentation manager at Olimex