NRESET pin of ARM-USB-OCD-H stuck at 0

Started by xav, January 23, 2020, 01:54:36 pm

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We've been using quite extensively the ARM-USB-OCD-H JTAG probe.
However, several of them have failed after some time with the same symptom :
the NRESET pin (system reset, pin #15) suddenly stops working as expected and permanently pulls NRESET to 0.
As far as we know, the pin is not subjected to any stress that could damage it in our board designs.
is this a known weakness of those probes ?  Is there any specific precaution we should take ?
(what we do quite commonly is unplug/re-plug the other end of the USB cable connecting to the probe).

Thanks for any hint,


Probably FET1 got damaged. It is N-channel MOSFET BSS123 in SOT23 package. Replace it if possible and check again. Let me know how it goes.

This happens quite likely due to electrostatic influence. Do you use rubber gloves and avoid improper clothing when handling the boards that need to be programmed?

I have relayed your report to the hardware team but I am not sure if anything can be done in the long run.
Technical support and documentation manager at Olimex


Ok we'll try that and let you know.
I must admit we haven't always worn anti-static wristbands or gloves. Having said that, the rate of occurence seems really high for an ESD issue. Also I'm pretty sure, in several cases at least, it just stopped working while we didn't touch anything else than the cables.


Just tell me if replacing FET1 solves it, if it doesn't it is probably something else. I can give you some further advice once I know that.
Technical support and documentation manager at Olimex


Finally getting round to feed-backing on that :

We removed that BSS123 NFET on a few of our broken Olimex and... it works, we're again able to program boards with those probes !
Actually it works without even replacing the FET, which as far as I understand means the probe cannot drive NRESET anymore. Not sure if there's nevertheless a risk JTAG might sometimes not start properly if NRESET isn't asserted before trying to establish a connection, as is then the case.

Still, the big question is: how come that NRESET pin (pin 15, SRST_N system reset) gets broken so often ??
On our board that pin just connects to a pull-up (10K to 50K) to VDD, the target voltage also provided to pin 1 of the probe.



It is just FET1 is sensitive and can be damaged by external influence. It probably gets damaged by static electricity or some other influence during plug/unplug. The gate of FET1 goes to pin #15 via 100R.

We are considering improving this part of design for the next hardware revision.
Technical support and documentation manager at Olimex


Thanks for the feedback -

SRST_N is an output of the probe towards the target chip, right ?

So, as you're saying the gate of FET1 goes to pin #15 (SRST_N), it's not FET1 that's driving this pin, rather FET1 is controlled by the SRST_N signal, which is provided by some other gate of your probe. Correct ?

Also, one side question please:
so far I'd assumed that the SRST_N output is open-drain (to allow wire-ANDing of SRST_N with e.g. a signal from some h/w reset push button on the target board). Is this the case ?
And what about regular JTAG signals (TDI, etc)-- regular push-pull CMOS ?