DDR3 routing on Olinuxino-A64

Started by zharry, December 07, 2019, 03:05:21 PM

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Hi, couple of questions again.
1. I am looking at the KiCAD PCB file and it seems there is as much as 3.7mm difference for Address / Control bank traces. Is that because of pad compensation or does it not matter to have them matched under 2mm (under 10ps) so much?

2. If it's pad delay, can you point me to a datasheet or some resource where I can look those up?

3. I could not the stackup for PCB in github project. Is anyone able / willing to share this info?

Thanks, Harry.


Also, I see that last data group has 2 times shorter traces than other data groups - so there is some memory controller configuration somewhere to deal with it? Where would that be located and how do I change it?


Hi Harry,

Were you able to find the answer to your questions? I have the same ones.