November 22, 2019, 09:14:44 am

ice40HX8k-EVB constraint file

Started by Forty-Bot, March 19, 2019, 06:11:49 am

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Forty-Bot

March 19, 2019, 06:11:49 am Last Edit: March 19, 2019, 06:42:04 am by Forty-Bot
I made a pcf so you don't have to. Contains all named pins on the board (not including the large headers). Note that you can have duplicate net -> pin mappings as long as you don't try to connect multiple nets to one pin. So if your top-level verilog file looks like

module top (hwclk);
  input hwclk;
  /* ... */
endmodule


Then you can modify the pcf to look like


# Clock
set_io -nowarn SYSCLK J3 # GBIN6
set_io -nowarn hwclk J3


and it will still pnr fine