Extension header pins on ESP32-Gateway

Started by pettus, February 15, 2019, 08:35:43 am

Previous topic - Next topic

pettus

I am gathering a collection of ESP32-Gateway boards to interface with various serial devices.  I just recently needed to use SPI, and got am confused at the choice of GPIOs connected to the headers.

Previously I used I2C - defaults to pins GPIO 16 and 17, easy.

Now with SPI the default pins aren't available on the header, weird but easily bypassed in software.  But when choosing the pins to use I discovered that of 20 header pins, 5 are fixed to non-GPIO, 6 are GPIO but you aren't supposed to use them because they're debug only and mess with the flash, 4 are GPI (not O), and only 5 are actually available for true general use (I guess my MISO pin can use a GPI, so I'll only use 3/5 of my GPIOs for my SPI bus).  What about when I have a project that wants to use two SPI buses concurrently?

I must be thinking about this wrong, because this seems like a strange design choice.

Are there any caveats to using these headers?  I have a rev C board so the PHY power isn't linked to pin4/GPIO5, but otherwise would that mess with my RJ45 ethernet connection?

(I started this as a GitHub issue, but it's probably more suitable to discussion here, sorry for the duplication of https://github.com/OLIMEX/ESP32-GATEWAY/issues/9)