Olimex Support Forum

ARM => ST => Topic started by: MarcC137 on July 10, 2021, 11:30:01 pm

Title: STM32MP1 schematic
Post by: MarcC137 on July 10, 2021, 11:30:01 pm
I've noticed that the schematic for the STM32MP1 has the DDR lines not in order.

i.e. DQL0 -> DQ5 | DQL1 -> DQ1 ...

Is this correct?
Title: Re: STM32MP1 schematic
Post by: LubOlimex on July 12, 2021, 12:52:08 pm
Yes, it is correct. You can misarrange the bits in the byte.
Title: Re: STM32MP1 schematic
Post by: MarcC137 on July 15, 2021, 01:05:00 am
Oh OK thanks, learned something new.