Olimex Support Forum

OLinuXino Android / Linux boards and System On Modules => AM3352 => Topic started by: TomKnights on December 10, 2015, 11:08:32 am

Title: AM3352 DDR3 EMIF Setup Register Values
Post by: TomKnights on December 10, 2015, 11:08:32 am
Hello All,

I'm using the Olimex AM3352 SOM, with the TI StarterWare source code, so that I don't need linux, and can get the most performance out of the CPU.

I have already tried to use the StarterWare code for detecting the DDR3 settings but it didn't work.
I have also tried calculating the values from the DDR3 data sheet (I have a degree in electronics, so I'm not a newbie)
I have corrected the memory size problem (256->512MB) but I get read and write errors.
I have coded a memory test into the boot loader which shows this.
I have also coded a small serial command handler so I can change the values while it's running.

These are the default values (which don't work, some lines have commented out values in brackets which are the calculated values from the TI spreadsheet):
// these are all dependant on the board layout, so are the same for all Olimex AM3352 SOM's
// But I cannot calculate them by self, my JTAG programmer isn't compatible with CCS
#define DDR3_CMD0_SLAVE_RATIO_0            (0x40)
#define DDR3_CMD0_INVERT_CLKOUT_0          (0x1)
#define DDR3_CMD1_SLAVE_RATIO_0            (0x40)
#define DDR3_CMD1_INVERT_CLKOUT_0          (0x1)
#define DDR3_CMD2_SLAVE_RATIO_0            (0x40)
#define DDR3_CMD2_INVERT_CLKOUT_0          (0x1)

#define DDR3_DATA0_RD_DQS_SLAVE_RATIO_0    (0x3B)
#define DDR3_DATA0_WR_DQS_SLAVE_RATIO_0    (0x85)
#define DDR3_DATA0_FIFO_WE_SLAVE_RATIO_0   (0x100)
#define DDR3_DATA0_WR_DATA_SLAVE_RATIO_0   (0xC1)

#define DDR3_DATA0_RD_DQS_SLAVE_RATIO_1    (0x3B)
#define DDR3_DATA0_WR_DQS_SLAVE_RATIO_1    (0x85)
#define DDR3_DATA0_FIFO_WE_SLAVE_RATIO_1   (0x100)
#define DDR3_DATA0_WR_DATA_SLAVE_RATIO_1   (0xC1)

// These should be OK
#define DDR3_CONTROL_DDR_CMD_IOCTRL_0      (0x18B)
#define DDR3_CONTROL_DDR_CMD_IOCTRL_1      (0x18B)
#define DDR3_CONTROL_DDR_CMD_IOCTRL_2      (0x18B)

#define DDR3_CONTROL_DDR_DATA_IOCTRL_0      (0x18B)
#define DDR3_CONTROL_DDR_DATA_IOCTRL_1      (0x18B)

//#define DDR3_CONTROL_DDR_IO_CTRL           (0x0fffffff)
#define DDR3_CONTROL_DDR_IO_CTRL           (0xffffffff) // 0xefffffff

#define DDR3_EMIF_DDR_PHY_CTRL_1           (0x06)
#define DDR3_EMIF_DDR_PHY_CTRL_1_DY_PWRDN         (0x00100000)
#define DDR3_EMIF_DDR_PHY_CTRL_1_SHDW      (0x06)
#define DDR3_EMIF_DDR_PHY_CTRL_1_SHDW_DY_PWRDN    (0x00100000)
#define DDR3_EMIF_DDR_PHY_CTRL_2           (0x06)

// These most likely aren't
#define DDR3_EMIF_SDRAM_TIM_1              (0x0888A39B) //m(0x0AAAE51B)
#define DDR3_EMIF_SDRAM_TIM_1_SHDW         (0x0888A39B) //m(0x0AAAE51B)

#define DDR3_EMIF_SDRAM_TIM_2              (0x26337FDA) //(0x4A6B7FDA) //()
#define DDR3_EMIF_SDRAM_TIM_2_SHDW         (0x26337FDA) //(0x4A6B7FDA) //()

#define DDR3_EMIF_SDRAM_TIM_3              (0x501F830F) //(0x501F867F) //()
#define DDR3_EMIF_SDRAM_TIM_3_SHDM         (0x501F830F) //(0x501F867F) //(0x501F830F)

#define DDR3_EMIF_SDRAM_REF_CTRL_VAL1      (0x0000093B) // (3120)
#define DDR3_EMIF_SDRAM_REF_CTRL_SHDW_VAL1 (0x0000093B) // (3120)

#define DDR3_EMIF_ZQ_CONFIG_VAL            (0x50074BE4)
#define DDR3_EMIF_SDRAM_CONFIG             (0x61C04B32) // fixed no of row address lines. Was (0x61C04AB2)
                                                        //(0x61C04AB2)termination = 1 (RZQ/4)
                                                       //dynamic ODT = 2 (RZQ/2)
                                                       //SDRAM drive = 0 (RZQ/6)
                                                       //CWL = 0 (CAS write latency = 5)
                                                       //CL = 2 (CAS latency = 5)
                                                       //ROWSIZE = 5 (14 row bits)
                                                       //PAGESIZE = 2 (10 column bits)

If someone perform the TI DDR3 calculations using CCS and the required JTAG programmer, I would be most grateful!
These are the two webpages you need.


Due to a silicon error in the AM3352 I cannot read all the values out of a running linux distro. Also I don't think the kernel would let you access them anyway.
I have considered disassembling the boot loader on the supplied debian image.


Title: Re: AM3352 DDR3 EMIF Setup Register Values
Post by: TomKnights on December 10, 2015, 11:12:20 am
Also will the DDR3 run at it's fully rated 400MHz clock speed? If so please calculate the register values for this speed.
Title: Re: AM3352 DDR3 EMIF Setup Register Values
Post by: Chester Gillon on December 11, 2015, 01:49:59 am
I have been using StartWare on the AM3352.
https://github.com/Chester-Gillon/AM3352-SOM-EVB_bare_metal/blob/master/gel_files/AM3352_SOM.gel (https://github.com/Chester-Gillon/AM3352-SOM-EVB_bare_metal/blob/master/gel_files/AM3352_SOM.gel) is a GEL script which contains the DDR3 settings used, and how there were derived.

https://github.com/Chester-Gillon/AM3352-SOM-EVB_bare_metal/blob/master/bootloader/bl_platform.c (https://github.com/Chester-Gillon/AM3352-SOM-EVB_bare_metal/blob/master/bootloader/bl_platform.c) is a modified bootloader for the AM3352 which also contains the same DDR3 settings, in the #ifdef AM3352_SOM parts of the code.

The DDR3 is run at a 400MHz clock speed, and DDR3 tests have been run which didn't report any errors.
Title: Re: AM3352 DDR3 EMIF Setup Register Values
Post by: TomKnights on December 11, 2015, 01:49:08 pm
WOW! Thank you very much.

I have replaced R44 (on the same side as the AM3352, near U6) from 1.1K to 1.0K to make V1.25 -> V1.32 so I can use 1GHz (Nitro mode).

I don't use CCS, I have IAR ARM, so I cannot use gel files.
However I have used your DDR3 register settings @400MHz and it's all working perfectly.
I have ran multiple memory tests on the whole DDR3 memory range and all tests pass.

Thanks again.