December 07, 2021, 07:41:51 pm

STM32MP1 schematic

Started by MarcC137, July 10, 2021, 11:30:01 pm

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MarcC137

I've noticed that the schematic for the STM32MP1 has the DDR lines not in order.

i.e. DQL0 -> DQ5 | DQL1 -> DQ1 ...

Is this correct?

LubOlimex

Yes, it is correct. You can misarrange the bits in the byte.
Technical support and documentation manager at Olimex

MarcC137

Oh OK thanks, learned something new.