I've just updated my E80 CPU project for the GateMateA1-EVB

[Stokpan]

Hi everyone,

A few months ago, I completed my undergraduate thesis demonstrating that a CPU in VHDL for educational purposes is feasible using only the elementary digital design theory taught at my university. Along with the CPU, I wrote an assembler and created an environment that allows for assembly programming and simulation via GHDL with a single hotkey.

The CPU was tested on three EDAs and two FPGA boards. One of the GHDL developers recommended I try the Olimex GateMateA1-EVB, and I am glad I did.

I have spent the last month working to bring the E80 to this platform. Although the CPU is simple, the design is based 100% on structural VHDL and flip-flops; it is "novel" enough that EDAs often cannot infer their own optimized components, making it a great stress test for the open-source tools.

The hardest part was getting a stable flow running on Windows. I encountered several inconsistencies:

• The Programmer: The openFPGALoader included in the latest oss-cad-suite failed to upload—the config LED would flash for a fraction of a second, but the bitstream wouldn't stick. I found that the version in the older cc-toolchain-win package works perfectly.
• The P&R: Conversely, the older p_r utility struggled with my design, whereas the new nextpnr-himbaechel in the oss-cad-suite works flawlessly.
• The Driver: The recommended driver installation guidelines didn't work in my tests, and I had to find the correct driver from the Zadig utility by trial-and-error.
• VHDL Elaboration: Most recommended Yosys-GHDL combinations seem optimized for single-file designs. Since my project uses multiple files and custom libraries, I had to implement a specific sequence using GHDL for elaboration and Yosys for synthesis.

I also found that many existing toolchain scripts for Windows are overly complicated, often requiring subsequent runs of the same batch file with different options just to finish a build.

I worked hard to make this process as smooth as possible for the end user, providing a "one-click" batch flow that handles the version mixing and multi-file synthesis automatically. You can find the detailed setup and the Windows-specific instructions here:

https://github.com/Stokpan/E80?tab=readme-ov-file#example-3---testing-on-the-olimex-gatematea1-evb-on-windows

(Yes, I didn't use resistors for the LEDs. Two reasons: this build will soon be replaced by serial output, and I have partial color blindness which makes it really difficult to see the LEDs without full brightness)

Hopefully, this work helps other authors and students support this great and cost-effective board!

[LubOlimex]

This is great thank you for posting it! I myself had some trouble getting the environment setup properly under Windows.

[Stokpan]

I think the main reason for the difficulty is that the OSS-CAD suite builds for Windows do not include the GHDL plugin for Yosys. But that wasn't really necessary, all I had to do was to elaborate the project folder and a single board-specific VHDL file with GHDL and output the whole thing into a single Verilog file. After that the process is typical...

...well not so typical because I also had to find the correct driver by trial and error and also discover that the openfpgaloader in the OSS-CAD suite doesn't work whereas the one in the old Gatemate suite does.

If anyone wants a helping hand understanding my synth.bat file, let me know -- I'll be watching this topic.