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Author Topic: Good time to get onboard the RISC-V train  (Read 161 times)

Morgaine

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Good time to get onboard the RISC-V train
« on: May 27, 2019, 05:41:42 PM »
RISC-V is a rapidly rising star in the open embedded world, an answer to FOSS's long-standing desire for a CPU architecture that is open down to the gate level, and without royalties for use.

There aren't many embedded board providers in the RISC-V market yet, so now would be a good time to establish a presence in that community and benefit from all the buzz, enthusiasm and good PR that surrounds it.  For example, there are RISC-V presentations given regularly at conferences, and unlike proprietary architectures, active adopters can influence the direction taken in both hardware and software.  What's more, the political and industrial worries about backdoors in proprietary CPUs these days provide an additional reason for widespread interest in RISC-V.

I was prompted to post this because a significant player in embedded boards (Seeed) has become active in RISC-V and is gaining a lot of good PR from it.  They already have several products which use Indiegogo-funded Sipeed MAix M1 modules containing the dual-core 64-bit RISC-V Kendryte K210 microcontroller plus neural network hardware, and in June they're releasing a version in RPi HAT format that will give them huge exposure in the Pi community.  Here are a few relevant links to save you time:


Olimex already has a good reputation in FOSS and OSHW circles, so providing one or more RISC-V products would seem like a natural direction to take.  Given that Seeed resells the Sipeed MAiX-I module for a mere $7.90, the Sipeed device might be a good basis for Olimex products as well.  It's in the ESP32 price ballpark but adds powerful RISC-V and neural network capability, and could add more OSHW diversity to your IoT range.

Morgaine.

olimex

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Re: Good time to get onboard the RISC-V train
« Reply #1 on: May 29, 2019, 08:11:11 AM »
Hi Morgaine,

I'm also very enthusiastic about RISC-V and the ability to have truly open silicone, but from what I see now it's still long shot until we got it.

These Chinese RISC-V adopters use the RISC-V MIT Licensee just to release not open SOC designs.

So I'm asking myself is there really advantage to use Chinese RISC-V SOC which is closed source design the same way or even the worse than Chinese ARM SOC? ARM at least restricts you to use just one instruction set while RISC-V allow you to make your own instruction mess, which will make all these "RISC-V" SOC non code compatible if bought from different vendors.

It's like iOS which uses Open source BSD code, but is closed source product, so what is the advantage to use these RISC-V non open silicons vs ARM non open silicons made in China?

Correct me if I'm wrong, but there is no any public data about K210 internals, which makes the RISC-V name just OSHW buzz word with no any open source hardware coverage. So nobody knows what is inside.

Snip from https://riscv.org/faq/

"3. If our company builds a RISC-V implementation, is it required to release its source code for the RISC-V core?
No, the source code can be completely closed"

Thanks
Tsvetan