JTAG tap: at91sam7s.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3)
srst pulls trst - can not reset into halted mode. Issuing halt after reset.
target state: halted
target halted in Thumb state due to debug-request, current mode: Supervisor
cpsr: 0x200000f3 pc: 0x000001fc
requesting target halt and executing a soft reset
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x200000d3 pc: 0x00000000
Bad value '00000001' captured during DR or IR scan:
check_value: 0x00000009
check_mask: 0x00000009
JTAG error while reading cpsr
in procedure 'reset'
in procedure 'ocd_bouncer'
in procedure 'ocd_process_reset'
in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 248
in procedure 'at91sam7s.cpu' called at file "embedded:startup.tcl", line 370
in procedure 'ocd_bouncer'
I don't think that AT91SAM7 can reset in halt... AT91SAM7 can't reset in halt, this means that it will execute code in Flash before any JTAG debugger can halt the chip.
Best to use soft_reset_halt whenever possible and use "reset init" only when JTAG gets out of sync, i.e. when target is power-cycled.
Again I recommend you to use the openocd mail lists. You won't find OpenOCD experts here.