Hi,
I'm trying to get JTAG working on a board which as cs3516 arm with spansion flash. It has a 20-pin JTAG port. This is what I get when I fire up openocd. I tried by reducing the adapter clock upto 0 but I still get these errors/warn. The target reset doesn't work. I think a proper JTAG connection should give JTAG TAP Info. Any idea what could be wrong here and how to fix?
openocd -f interface/olimex-arm-usb-ocd-h.cfg -f target/cs351x.cfg
Open On-Chip Debugger 0.6.1 (2013-05-04-20:46)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
adapter speed: 500 kHz
dcc downloads are enabled
Info : max TCK change to: 30000 kHz
Info : clock speed 500 kHz
Error: JTAG scan chain interrogation failed: all ones
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway...
Error: cs351x.cpu: IR capture error; saw 0x0f not 0x01
Warn : Bypassing JTAG setup events due to errors
Info : Embedded ICE version 15
Error: unknown EmbeddedICE version (comms ctrl: 0xffffffff)
Info : cs351x.cpu: hardware has 2 breakpoint/watchpoint units
Error: fa526_change_to_arm: there is no Thumb state on FA526
Warn : ThumbEE -- incomplete suppor
(gdb) mon targets
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* cs351x.cpu fa526 little cs351x.cpu halted
Hello,
Maybe you can try with the new openocd-0.7.0 and then see if there is still an issue?
http://openocd.sourceforge.net/
Best Regards,
Maria/OLIMEX
Thanks Maria. I tried the OpenOCD 0.7.0 version and I got the same errors. I think the JTAG circuit is not open for some reason. Maybe proper timing, SRST signals, speed have to be setup to open the circuit.
Hey jtagkit,
Can you, please, direct us to some datasheet of the board you use or the microcontroller you use?
Best regard,
Lub/OLIMEX
Hey Lub,
Thanks for pitching in. Unfortunately there are no datasheets of the board and the SoC available that I could find. The board is from Alpha Networks and the SoC is Cortina CS3516 which is based on the FA256 ( ARM920T/Armv4 variant ). I guess RST needs to be asserted with nTRST reset. I tried some combinations of these signals but nothing worked. I guess RST is open and unless it's asserted manually it's not gonna work.
Hey jtagkit,
There are different reset strategies in OpenOCD. These can be edited in the .cfg files. Please check here: http://openocd.sourceforge.net/doc/html/Reset-Configuration.html (http://openocd.sourceforge.net/doc/html/Reset-Configuration.html).
Best regards,
Lub/OLIMEX
Thanks Lub. I've tried various reset config combinations but they didn't help.
I think I'll have to check the JTAG signals to see what's going on. I'll look for a good logic analyzer supporting JTAG protocol.
Thanks