I made a pcf (https://gist.github.com/ea32c43c0e451ffe0eb155cc14305947) so you don't have to. Contains all named pins on the board (not including the large headers). Note that you can have duplicate net -> pin mappings as long as you don't try to connect multiple nets to one pin. So if your top-level verilog file looks like
module top (hwclk);
input hwclk;
/* ... */
endmodule
Then you can modify the pcf to look like
# Clock
set_io -nowarn SYSCLK J3 # GBIN6
set_io -nowarn hwclk J3
and it will still pnr fine