Hello,
i am trying to use the clk_out_a and _b signals on PI12 and PI13.
This signals seems to be open drain, is this right? If i use the internal pull-up i get a very shallow rising edge but a steep falling one. Without pull up/down i get nothing.
The serial output funktion generates steep edges without any problem on this pins. So, is the clock signal always open drain or are there some settings, additionally to PIO mux, driver level and pull up/down?
Thanks.