hi
in schematic that is for A13-OLinuXino and in tracks that is for u2 component (H5TQ2G83CFR-H9C) why nets that is for data (D8.....D15) is not respectively connected to DQ0 .... DQ7
connection nets in dram u2 is :
DQ0 ———-> D15
DQ1 ———-> D12
DQ2 ———-> D13
DQ3 ———-> D8
DQ4 ———-> D11
DQ5 ———-> D10
DQ6 ———-> D9
DQ7 ———-> D14
shell it be like this ?????
DQ0 ———-> D8
DQ1 ———-> D9
DQ2 ———-> D10
DQ3 ———-> D11
DQ4 ———-> D12
DQ5 ———-> D13
DQ6 ———-> D14
DQ7 ———-> D15
in ddr3 sdram u1 data pin connection is correct but in ddr3 sdram u2 confuse and data pin is unregular please help me
The operating system is defined as؟؟؟
I am confused please help me
There's nothing wrong with that: data are written in 'mixed order' ( from our point of view ) and then read back using the same 'mixed order', so everything goes to the right place
very tanks davidefa for your answer
so in A13-OLinuXino-MICRO board data pins of dram is regular (D0....D15 connected to DQ0....DQ15) because only one dram used and defined by in os (mixed order)
so why in A13-OLinuXino-MICRO board This method is not used
Hi all friends
I've designed a board based on the schematic A13-OLinuXino
After assembling the board all things was good (Output of voltage regulators and connection parts )
i download This image (A13_debian_34_75_WIFI_GCC_GPIO_X_I2C_100KHz_UVC_TS_video_release_8.img) and write it on the sd card and connect usb2serial cable to usart1 and power up the board after power up not Happened anythings and I have seen on hyperterm :
QuoteU-Boot SPL 2012.10-04259-g832a8e5 (Nov 08 2012 - 06:49:37)
DRAM: ? ? 0MB
### ERROR ### Please RESET the board ###
somehow a13 Did not see dram
on my dram write skhynix that Difference with hynix that used on A13-OLinuXino board but part number Both dram is H5TQ2G83CFR-H9C
This problem could be the sd card Quality or the dram type or Impedance matching for dram data bus Routing ???
Who knows where it could be problem?
anyone can not help me :-\