Hi,
My FPGA design becomes unstable when I fill the FPGA like 50% with a compute intensive design and have varying loads.
I was wondering whether the power supply could cause this an checked the schematic. I found that the capacitors on the VDD pins are much smaller than what CologneChip is using in their Evaluation board. For instance, Olimex uses plenty of 1nF capacitors which seems very optimistic from my point of view.
The chain of capacitors being 2.2uF, 100nF, multiple 1nF.
In contrast the CologneChip board:
2.2uF, 470nF, 2x 100nF, 2x 10nF.
Could this be causing the issues I'm seeing?
I didn't use the SERDES yet, but also for the VDD_SER, the difference in dimensioning the capacitors is huge.
Thanks
Hello,
Can you check how is the VDD_CORE_SET1 jumper set? Is it as per default in position 2-1? Position 2-1 is "economy mode" and sets the voltage of the VDD core to 1.0V. This jumper is the rightmost at the bottom, just next to the UEXT1 connector.
Try to change it to position 3-2 (e.g. move it to the left two pins). This is "speed mode" and raises the voltage of the VDD core to 1.1V. Then test again.
Let me know if that fixes the issue.
Best regards,
Lub/OLIMEX
Hi Lub,
Thanks for your prompt response.
Actually, I'm running the board in speed mode already and I measured 1.098V.
The only thing I'm guilty of is running timing analysis in typical mode instead of worst mode. Otherwise I don't achieve timing closure, running the design at 50 MHz.
Still, the CologneChip board uses capacitors with much higher capacitance, not only for the core voltage but also for the IP banks and SERDES.
Best regards