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00008 #define Enable_external_clock() (CKSEL0 |= (1<<EXTE))
00009 #define Disable_external_clock() (CKSEL0 &= ~(1<<EXTE))
00010 #define Enable_RC_clock() (CKSEL0 |= (1<<RCE))
00011 #define Disable_RC_clock() (CKSEL0 &= ~(1<<RCE))
00012 #define External_clock_ready() (((CKSTA&(1<<EXTON)) != 0) ? TRUE : FALSE)
00013 #define RC_clock_ready() (((CKSTA&(1<<RCON)) != 0) ? TRUE : FALSE)
00014 #define Select_external_clock() (CKSEL0 |= (1<<CLKS))
00015 #define Select_RC_clock() (CKSEL0 &= ~(1<<CLKS))
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00018 #define Load_ext_clock_config(cfg) (CKSEL1 &= ~0x0F, CKSEL1 |= (cfg&0x0F))
00019 #define Load_RC_clock_config(cfg) (CKSEL1 &= ~0xF0, CKSEL1 |= (cfg&0xF0))
00020
00021 #define EXTCLK_8MHZ_AND_MORE 0x0F
00022 #define INTRC_8MHZ 0x20
00023
00024
00025 #define Clock_switch_external() { Enable_external_clock(); while (!External_clock_ready()); \
00026 Select_external_clock(); Disable_RC_clock(); }
00027 #define Clock_switch_internal() { Enable_RC_clock(); while (!RC_clock_ready()); \
00028 Select_RC_clock(); Disable_external_clock(); }
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00035 #define Usart_spi_hard_init() (PORTD |= 0x2C, DDRD |= 0x28, DDRD &= ~0x04)
00036 #define Usart_hard_init_without_ctrl() (PORTD |= 0x0C, DDRD |= 0x08, DDRD &= ~0x04)
00037 #define Usart_hard_init_with_ctrl() (PORTD |= 0xCC, DDRD |= 0x48, DDRD &= ~0x84)
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00040 #define Usart_spi_soft_init() (UBRR1 = 0, \
00041 UCSR1C = (1<<7)|(1<<6)|(1<<1)|(1<<0), \
00042 UCSR1B = (1<<3)|(1<<4), \
00043 UBRR1 = 4) // baudrate = 800kbits/s
00044 #define Usart_soft_init_with_ctrl() (UBRR1 = 0, \
00045 UCSR1C = (1<<UCSZ11) | (1<<UCSZ10), \
00046 UCSR1D = (1<<CTSEN) | (1<<RTSEN), \
00047 UCSR1B = (1<<RXEN1) | (1<<TXEN1), \
00048 UBRR1 = 9) // baudrate = 50kbits/s
00049
00050
00051 #define Usart_soft_init_without_ctrl() (UBRR1 = 0, \
00052 UCSR1C = (1<<UCSZ11) | (1<<UCSZ10), \
00053 UCSR1D &= ~((1<<CTSEN) | (1<<RTSEN)), \
00054 UCSR1B = (1<<RXEN1) | (1<<TXEN1), \
00055 UBRR1 = 4) // baudrate = 100kbits/s
00056
00057 #define Usart_write_byte(dt) (UDR1 = dt)
00058 #define Usart_read_byte() (UDR1)
00059 #define Is_usart_byte_sent() (((UCSR1A&(1<<TXC1)) != 0) ? TRUE : FALSE)
00060 #define Usart_clear_flag_send() (UCSR1A |= (1<<TXC1))
00061 #define Is_usart_byte_received() (((UCSR1A&(1<<RXC1)) != 0) ? TRUE : FALSE)
00062 #define Usart_clear_flag_receive() (UCSR1A |= (1<<RXC1))
00063 #define Is_usart_data_reg_empty() (((UCSR1A&(1<<UDRE1)) != 0) ? TRUE : FALSE)
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00067 #define USE_TIMER16 TIMER16_1 // needed if the delay macros written below are used
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00071 #define Delay_config_ms(ms) (Timer16_set_clock(TIMER16_CLKIO_BY_256), \
00072 Timer16_set_mode_output_a(TIMER16_COMP_MODE_NORMAL), \
00073 Timer16_set_waveform_mode(TIMER16_WGM_CTC_OCR), \
00074 Timer16_set_compare_a((U16)(31)*(U16)(ms)))
00075 #define Delay_config_us(us) (Timer16_set_clock(TIMER16_CLKIO_BY_8), \
00076 Timer16_set_mode_output_a(TIMER16_COMP_MODE_NORMAL), \
00077 Timer16_set_waveform_mode(TIMER16_WGM_CTC_OCR), \
00078 Timer16_set_compare_a((U16)(us)))
00079
00080 #define Delay_reset() (Timer16_set_counter(0x0000), Timer16_clear_compare_a_it())
00081 #define Is_delay_end() (Timer16_get_compare_a_it())
00082 #define Is_not_delay_end() (!(Timer16_get_compare_a_it()))
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00087 #define Bp_delay_debounce() { Delay_config_ms(20); Delay_reset(); while (Is_not_delay_end());}
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