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00012 #ifndef MCU_H
00013 #define MCU_H
00014
00015
00016
00017
00018
00019
00020 #if defined(__ICCAVR__) || defined(__IAR_SYSTEMS_ASM__)
00021
00022
00023 SFR_B(PINB, 0x03)
00024 SFR_B(DDRB, 0x04)
00025 SFR_B(PORTB, 0x05)
00026
00027 SFR_B(PINC, 0x06)
00028 SFR_B(DDRC, 0x07)
00029 SFR_B(PORTC, 0x08)
00030
00031 SFR_B(PIND, 0x09)
00032 SFR_B(DDRD, 0x0A)
00033 SFR_B(PORTD, 0x0B)
00034
00035 SFR_B(TIFR0, 0x15)
00036 SFR_B(TIFR1, 0x16)
00037
00038 SFR_B(PCIFR, 0x1B)
00039
00040 SFR_B(EIFR, 0x1C)
00041 SFR_B(EIMSK, 0x1D)
00042
00043 SFR_B(GPIOR0, 0x1E)
00044
00045 SFR_B(EECR, 0x1F)
00046 SFR_B(EEDR, 0x20)
00047 SFR_W(EEAR, 0x21)
00048
00049 SFR_B(GTCCR, 0x23)
00050
00051 SFR_B(TCCR0A, 0x24)
00052 SFR_B(TCCR0B, 0x25)
00053 SFR_B(TCNT0, 0x26)
00054 SFR_B(OCR0A, 0x27)
00055 SFR_B(OCR0B, 0x28)
00056
00057 SFR_B(PLLCSR, 0x29)
00058
00059 SFR_B(GPIOR1, 0x2A)
00060 SFR_B(GPIOR2, 0x2B)
00061
00062 SFR_B(SPCR, 0x2C)
00063 SFR_B(SPSR, 0x2D)
00064 SFR_B(SPDR, 0x2E)
00065
00066 SFR_B(ACSR, 0x30)
00067
00068 SFR_B(DWDR, 0x31)
00069
00070 SFR_B(SMCR, 0x33)
00071 SFR_B(MCUSR, 0x34)
00072 SFR_B(MCUCR, 0x35)
00073
00074 SFR_B(SPMCSR, 0x37)
00075
00076 SFR_W(SP, 0x3D)
00077 SFR_B(SREG, 0x3F)
00078
00079 SFR_B_EXT(WDTCR, 0x60)
00080 SFR_B_EXT(WDTCSR, 0x60)
00081 SFR_B_EXT(CLKPR, 0x61)
00082 SFR_B_EXT(WDTCKD, 0x62)
00083
00084 SFR_B_EXT(REGCR, 0x63)
00085
00086 SFR_B_EXT(OSCCAL, 0x66)
00087
00088 SFR_B_EXT(PCICR, 0x68)
00089
00090 SFR_B_EXT(EICRA, 0x69)
00091 SFR_B_EXT(EICRB, 0x6A)
00092
00093 SFR_B_EXT(PCMSK0, 0x6B)
00094 SFR_B_EXT(PCMSK1, 0x6C)
00095
00096 SFR_B_EXT(TIMSK0, 0x6E)
00097 SFR_B_EXT(TIMSK1, 0x6F)
00098
00099 SFR_B_EXT(TCCR1A, 0x80)
00100 SFR_B_EXT(TCCR1B, 0x81)
00101 SFR_B_EXT(TCCR1C, 0x82)
00102 SFR_W_EXT(TCNT1, 0x84)
00103 SFR_W_EXT(ICR1, 0x86)
00104 SFR_W_EXT(OCR1A, 0x88)
00105 SFR_W_EXT(OCR1B, 0x8A)
00106 SFR_W_EXT(OCR1C, 0x8C)
00107
00108 SFR_B_EXT(UCSR1A, 0xC8)
00109 SFR_B_EXT(UCSR1B, 0xC9)
00110 SFR_B_EXT(UCSR1C, 0xCA)
00111 SFR_B_EXT(UCSR1D, 0xCB)
00112 SFR_W_EXT(UBRR1, 0xCC)
00113 SFR_B_EXT(UDR1, 0xCE)
00114
00115
00116
00117
00118
00119 SFR_B_EXT(USBCON, 0xD8);
00120 SFR_B_EXT(UDPADDL, 0xDB);
00121 SFR_B_EXT(UDPADDH, 0xDC);
00122
00123
00124
00125 SFR_B_EXT(UDCON, 0xE0);
00126 SFR_B_EXT(UDINT, 0xE1);
00127 SFR_B_EXT(UDIEN, 0xE2);
00128 SFR_B_EXT(UDADDR, 0xE3);
00129 SFR_B_EXT(UDFNUML, 0xE4);
00130 SFR_B_EXT(UDFNUMH, 0xE5);
00131 SFR_B_EXT(UDMFN, 0xE6);
00132 SFR_B_EXT(UDTST, 0xE7);
00133
00134
00135
00136 SFR_B_EXT(UENUM, 0xE9);
00137 SFR_B_EXT(UERST, 0xEA);
00138 SFR_B_EXT(UECONX, 0xEB);
00139 SFR_B_EXT(UECFG0X, 0xEC);
00140 SFR_B_EXT(UECFG1X, 0xED);
00141 SFR_B_EXT(UESTA0X, 0xEE);
00142 SFR_B_EXT(UESTA1X, 0xEF);
00143 SFR_B_EXT(UEINTX, 0xE8);
00144 SFR_B_EXT(UEIENX, 0xF0);
00145 SFR_B_EXT(UEDATX, 0xF1);
00146 SFR_B_EXT(UEBCLX, 0xF2);
00147 SFR_B_EXT(UEINT, 0xF4);
00148
00149
00150 SFR_B_EXT(PS2CON, 0xFA);
00151 SFR_B_EXT(UPOE, 0xFB);
00152
00153
00154 SFR_B_EXT(CKSEL0, 0xD0);
00155 SFR_B_EXT(CKSEL1, 0xD1);
00156 SFR_B_EXT(CKSTA, 0xD2);
00157
00158
00159
00160
00161
00162
00163 #define RESET_vect (0x00)
00164 #define INT0_vect (0x04)
00165 #define INT1_vect (0x08)
00166 #define INT2_vect (0x0C)
00167 #define INT3_vect (0x10)
00168 #define INT4_vect (0x14)
00169 #define INT5_vect (0x18)
00170 #define INT6_vect (0x1C)
00171 #define INT7_vect (0x20)
00172 #define PCINT0_vect (0x24)
00173 #define PCINT1_vect (0x28)
00174 #define USB_GENERAL_vect (0x2C)
00175 #define USB_ENDPOINT_vect (0x30)
00176 #define WDT_vect (0x34)
00177 #define TIMER1_CAPT_vect (0x38)
00178 #define TIMER1_COMPA_vect (0x3C)
00179 #define TIMER1_COMPB_vect (0x40)
00180 #define TIMER1_COMPC_vect (0x44)
00181 #define TIMER1_OVF_vect (0x48)
00182 #define TIMER0_COMPA_vect (0x4C)
00183 #define TIMER0_COMPB_vect (0x50)
00184 #define TIMER0_OVF_vect (0x54)
00185 #define SPI_STC_vect (0x58)
00186 #define USART1_RXC_vect (0x5C)
00187 #define USART1_UDRE_vect (0x60)
00188 #define USART1_TXC_vect (0x64)
00189 #define ANA_COMP_vect (0x68)
00190 #define EE_RDY_vect (0x6C)
00191 #define SPM_RDY_vect (0x70)
00192
00193
00194 #endif
00195
00196 #ifdef __CODEVISIONAVR__
00197
00198
00199 #define PINB (*(volatile unsigned char *)0x23)
00200 #define DDRB (*(volatile unsigned char *)0x24)
00201 #define PORTB (*(volatile unsigned char *)0x25)
00202
00203 #define PINC (*(volatile unsigned char *)0x26)
00204 #define DDRC (*(volatile unsigned char *)0x27)
00205 #define PORTC (*(volatile unsigned char *)0x28)
00206
00207 #define PIND (*(volatile unsigned char *)0x29)
00208 #define DDRD (*(volatile unsigned char *)0x2A)
00209 #define PORTD (*(volatile unsigned char *)0x2B)
00210
00211 #define TIFR0 (*(volatile unsigned char *)0x35)
00212 #define TIFR1 (*(volatile unsigned char *)0x36)
00213
00214 #define PCIFR (*(volatile unsigned char *)0x3B)
00215
00216 #define EIFR (*(volatile unsigned char *)0x3C)
00217 #define EIMSK (*(volatile unsigned char *)0x3D)
00218
00219 #define GPIOR0 (*(volatile unsigned char *)0x3E)
00220
00221 #define EECR (*(volatile unsigned char *)0x3F)
00222 #define EEDR (*(volatile unsigned char *)0x40)
00223 #define EEAR (*(volatile unsigned int *)0x41)
00224
00225 #define GTCCR (*(volatile unsigned char *)0x43)
00226
00227 #define TCCR0A (*(volatile unsigned char *)0x44)
00228 #define TCCR0B (*(volatile unsigned char *)0x45)
00229 #define TCNT0 (*(volatile unsigned char *)0x46)
00230 #define OCR0A (*(volatile unsigned char *)0x47)
00231 #define OCR0B (*(volatile unsigned char *)0x48)
00232
00233 #define PLLCSR (*(volatile unsigned char *)0x49)
00234
00235 #define GPIOR1 (*(volatile unsigned char *)0x4A)
00236 #define GPIOR2 (*(volatile unsigned char *)0x4B)
00237
00238 #define SPCR (*(volatile unsigned char *)0x4C)
00239 #define SPSR (*(volatile unsigned char *)0x4D)
00240 #define SPDR (*(volatile unsigned char *)0x4E)
00241
00242 #define ACSR (*(volatile unsigned char *)0x50)
00243
00244 #define DWDR (*(volatile unsigned char *)0x51)
00245
00246 #define SMCR (*(volatile unsigned char *)0x53)
00247 #define MCUSR (*(volatile unsigned char *)0x54)
00248 #define MCUCR (*(volatile unsigned char *)0x55)
00249
00250 #define SPMCSR (*(volatile unsigned char *)0x57)
00251
00252 #define SP (*(volatile unsigned int *)0x5D)
00253 #define SREG (*(volatile unsigned char *)0x5F)
00254
00255 #define WDTCR (*(volatile unsigned char *)0x60)
00256 #define CLKPR (*(volatile unsigned char *)0x61)
00257 #define OSCCAL (*(volatile unsigned char *)0x66)
00258
00259
00260 #define PCICR (*(volatile unsigned char *)0x68)
00261
00262 #define EICRA (*(volatile unsigned char *)0x69)
00263 #define EICRB (*(volatile unsigned char *)0x6A)
00264
00265 #define PCMSK0 (*(volatile unsigned char *)0x6B)
00266 #define PCMSK1 (*(volatile unsigned char *)0x6C)
00267
00268 #define TIMSK0 (*(volatile unsigned char *)0x6E)
00269 #define TIMSK1 (*(volatile unsigned char *)0x6F)
00270
00271 #define TCCR1A (*(volatile unsigned char *)0x80)
00272 #define TCCR1B (*(volatile unsigned char *)0x81)
00273 #define TCCR1C (*(volatile unsigned char *)0x82)
00274 #define TCNT1 (*(volatile unsigned int *)0x84)
00275 #define ICR1 (*(volatile unsigned int *)0x86)
00276 #define OCR1A (*(volatile unsigned int *)0x88)
00277 #define OCR1B (*(volatile unsigned int *)0x8A)
00278 #define OCR1C (*(volatile unsigned int *)0x8C)
00279
00280 #define UCSR1A (*(volatile unsigned char *)0xC8)
00281 #define UCSR1B (*(volatile unsigned char *)0xC9)
00282 #define UCSR1C (*(volatile unsigned char *)0xCA)
00283 #define UBRR1 (*(volatile unsigned int *)0xCC)
00284 #define UBRR1L (*(volatile unsigned char *)0xCC)
00285 #define UBRR1H (*(volatile unsigned char *)0xCD)
00286 #define UDR1 (*(volatile unsigned char *)0xCE)
00287
00288
00289
00290
00291 #define USBCON (*(volatile unsigned char *)0xD8)
00292 #define UDPADDL (*(volatile unsigned char *)0xDB)
00293 #define UDPADDH (*(volatile unsigned char *)0xDC)
00294
00295
00296
00297 #define UDCON (*(volatile unsigned char *)0xE0)
00298 #define UDINT (*(volatile unsigned char *)0xE1)
00299 #define UDIEN (*(volatile unsigned char *)0xE2)
00300 #define UDADDR (*(volatile unsigned char *)0xE3)
00301 #define UDFNUML (*(volatile unsigned char *)0xE4)
00302 #define UDFNUMH (*(volatile unsigned char *)0xE5)
00303 #define UDMFN (*(volatile unsigned char *)0xE6)
00304 #define UDTST (*(volatile unsigned char *)0xE7)
00305
00306
00307
00308 #define UENUM (*(volatile unsigned char *)0xE9)
00309 #define UERST (*(volatile unsigned char *)0xEA)
00310 #define UECONX (*(volatile unsigned char *)0xEB)
00311 #define UECFG0X (*(volatile unsigned char *)0xEC)
00312 #define UECFG1X (*(volatile unsigned char *)0xED)
00313 #define UESTA0X (*(volatile unsigned char *)0xEE)
00314 #define UESTA1X (*(volatile unsigned char *)0xEF)
00315 #define UEINTX (*(volatile unsigned char *)0xE8)
00316 #define UEIENX (*(volatile unsigned char *)0xF0)
00317 #define UEDATX (*(volatile unsigned char *)0xF1)
00318 #define UEBCLX (*(volatile unsigned char *)0xF2)
00319 #define UEINT (*(volatile unsigned char *)0xF4)
00320
00321
00322 #define PS2CON (*(volatile unsigned char *)0xFA)
00323 #define UPOE (*(volatile unsigned char *)0xFB)
00324
00325
00326 #define CKSEL0 (*(volatile unsigned char *)0xD0)
00327 #define CKSEL1 (*(volatile unsigned char *)0xD1)
00328 #define CKSTA (*(volatile unsigned char *)0xD2)
00329
00330
00331
00332
00333
00334
00335 #define RESET_vect 1
00336 #define INT0_vect 2
00337 #define INT1_vect 3
00338 #define INT2_vect 4
00339 #define INT3_vect 5
00340 #define INT4_vect 6
00341 #define INT5_vect 7
00342 #define INT6_vect 8
00343 #define INT7_vect 9
00344 #define PCINT0_vect 10
00345 #define PCINT1_vect 11
00346 #define USB_GENERAL_vect 12
00347 #define USB_ENDPOINT_vect 13
00348 #define WDT_vect 14
00349 #define TIMER1_CAPT_vect 15
00350 #define TIMER1_COMPA_vect 16
00351 #define TIMER1_COMPB_vect 17
00352 #define TIMER1_COMPC_vect 18
00353 #define TIMER1_OVF_vect 19
00354 #define TIMER0_COMPA_vect 20
00355 #define TIMER0_COMPB_vect 21
00356 #define TIMER0_OVF_vect 22
00357 #define SPI_STC_vect 23
00358 #define USART1_RXC_vect 24
00359 #define USART1_UDRE_vect 25
00360 #define USART1_TXC_vect 26
00361 #define ANA_COMP_vect 27
00362 #define EE_RDY_vect 28
00363 #define SPM_RDY_vect 29
00364
00365 #endif
00366
00367
00368
00369
00370
00371
00372
00373 #define PINB7 7
00374 #define PINB6 6
00375 #define PINB5 5
00376 #define PINB4 4
00377 #define PINB3 3
00378 #define PINB2 2
00379 #define PINB1 1
00380 #define PINB0 0
00381
00382
00383 #define DDB7 7
00384 #define DDB6 6
00385 #define DDB5 5
00386 #define DDB4 4
00387 #define DDB3 3
00388 #define DDB2 2
00389 #define DDB1 1
00390 #define DDB0 0
00391
00392
00393 #define PB7 7
00394 #define PB6 6
00395 #define PB5 5
00396 #define PB4 4
00397 #define PB3 3
00398 #define PB2 2
00399 #define PB1 1
00400 #define PB0 0
00401
00402
00403 #define PORTB7 7
00404 #define PORTB6 6
00405 #define PORTB5 5
00406 #define PORTB4 4
00407 #define PORTB3 3
00408 #define PORTB2 2
00409 #define PORTB1 1
00410 #define PORTB0 0
00411
00412
00413 #define PINC7 7
00414 #define PINC6 6
00415 #define PINC5 5
00416 #define PINC4 4
00417
00418 #define PINC2 2
00419 #define PINC1 1
00420 #define PINC0 0
00421
00422
00423 #define DDC7 7
00424 #define DDC6 6
00425 #define DDC5 5
00426 #define DDC4 4
00427
00428 #define DDC2 2
00429 #define DDC1 1
00430 #define DDC0 0
00431
00432
00433 #define PC7 7
00434 #define PC6 6
00435 #define PC5 5
00436 #define PC4 4
00437
00438 #define PC2 2
00439 #define PC1 1
00440 #define PC0 0
00441
00442
00443 #define PORTC7 7
00444 #define PORTC6 6
00445 #define PORTC5 5
00446 #define PORTC4 4
00447
00448 #define PORTC2 2
00449 #define PORTC1 1
00450 #define PORTC0 0
00451
00452
00453 #define PIND7 7
00454 #define PIND6 6
00455 #define PIND5 5
00456 #define PIND4 4
00457 #define PIND3 3
00458 #define PIND2 2
00459 #define PIND1 1
00460 #define PIND0 0
00461
00462
00463 #define DDD7 7
00464 #define DDD6 6
00465 #define DDD5 5
00466 #define DDD4 4
00467 #define DDD3 3
00468 #define DDD2 2
00469 #define DDD1 1
00470 #define DDD0 0
00471
00472
00473 #define PD7 7
00474 #define PD6 6
00475 #define PD5 5
00476 #define PD4 4
00477 #define PD3 3
00478 #define PD2 2
00479 #define PD1 1
00480 #define PD0 0
00481
00482
00483 #define PORTD7 7
00484 #define PORTD6 6
00485 #define PORTD5 5
00486 #define PORTD4 4
00487 #define PORTD3 3
00488 #define PORTD2 2
00489 #define PORTD1 1
00490 #define PORTD0 0
00491
00492
00493 #define OCF0B 2
00494 #define OCF0A 1
00495 #define TOV0 0
00496
00497
00498 #define ICF1 5
00499 #define OCF1C 3
00500 #define OCF1B 2
00501 #define OCF1A 1
00502 #define TOV1 0
00503
00504
00505 #define INTF7 7
00506 #define INTF6 6
00507 #define INTF5 5
00508 #define INTF4 4
00509 #define INTF3 3
00510 #define INTF2 2
00511 #define INTF1 1
00512 #define INTF0 0
00513
00514
00515 #define INT7 7
00516 #define INT6 6
00517 #define INT5 5
00518 #define INT4 4
00519 #define INT3 3
00520 #define INT2 2
00521 #define INT1 1
00522 #define INT0 0
00523
00524
00525 #define ISC31 7
00526 #define ISC30 6
00527 #define ISC21 5
00528 #define ISC20 4
00529 #define ISC11 3
00530 #define ISC10 2
00531 #define ISC01 1
00532 #define ISC00 0
00533
00534
00535 #define ISC71 7
00536 #define ISC70 6
00537 #define ISC61 5
00538 #define ISC60 4
00539 #define ISC51 3
00540 #define ISC50 2
00541 #define ISC41 1
00542 #define ISC40 0
00543
00544
00545 #define EEPM1 5
00546 #define EEPM0 4
00547 #define EERIE 3
00548 #define EEMWE 2
00549 #define EEWE 1
00550 #define EERE 0
00551
00552
00553 #define TSM 7
00554 #define PSR2 1
00555 #define PSR310 0
00556
00557
00558
00559 #define COM0A1 7
00560 #define COM0A0 6
00561 #define COM0B1 5
00562 #define COM0B0 4
00563 #define WGM01 1
00564 #define WGM00 0
00565
00566
00567 #define FOC0A 7
00568 #define FOC0B 6
00569 #define WGM02 3
00570 #define CS02 2
00571 #define CS01 1
00572 #define CS00 0
00573
00574
00575 #define SPIE 7
00576 #define SPE 6
00577 #define DORD 5
00578 #define MSTR 4
00579 #define CPOL 3
00580 #define CPHA 2
00581 #define SPR1 1
00582 #define SPR0 0
00583
00584
00585 #define SPIF 7
00586 #define WCOL 6
00587 #define SPI2X 0
00588
00589
00590 #define ACD 7
00591 #define ACBG 6
00592 #define ACO 5
00593 #define ACI 4
00594 #define ACIE 3
00595 #define ACIC 2
00596 #define ACIS1 1
00597 #define ACIS0 0
00598
00599
00600 #define DWR7 7
00601 #define DWR6 6
00602 #define DWR5 5
00603 #define DWR4 4
00604 #define DWR3 3
00605 #define DWR2 2
00606 #define DWR1 1
00607 #define DWR0 0
00608
00609
00610 #define SM2 3
00611 #define SM1 2
00612 #define SM0 1
00613 #define SE 0
00614
00615
00616 #define USBRF 5
00617 #define DWRF 4
00618 #define WDRF 3
00619 #define BORF 2
00620 #define EXTRF 1
00621 #define PORF 0
00622
00623
00624 #define DWD 7
00625 #define PUD 4
00626 #define IVSEL 1
00627 #define IVCE 0
00628
00629
00630 #define SPMIE 7
00631 #define RWWSB 6
00632 #define SIGRD 5
00633 #define RWWSRE 4
00634 #define BLBSET 3
00635 #define PGWRT 2
00636 #define PGERS 1
00637 #define SPMEN 0
00638
00639
00640 #define SP15 7
00641 #define SP14 6
00642 #define SP13 5
00643 #define SP12 4
00644 #define SP11 3
00645 #define SP10 2
00646 #define SP9 1
00647 #define SP8 0
00648
00649
00650 #define SP7 7
00651 #define SP6 6
00652 #define SP5 5
00653 #define SP4 4
00654 #define SP3 3
00655 #define SP2 2
00656 #define SP1 1
00657 #define SP0 0
00658
00659
00660 #define WDIF 7
00661 #define WDIE 6
00662 #define WDP3 5
00663 #define WDCE 4
00664 #define WDE 3
00665 #define WDP2 2
00666 #define WDP1 1
00667 #define WDP0 0
00668
00669
00670 #define WDEWIF 3
00671 #define WDEWIE 2
00672 #define WCLKD1 1
00673 #define WCLKD0 0
00674
00675
00676 #define CKLPCE 7
00677 #define CLKPCE 7 //for compatiblity
00678 #define CKLPS3 3
00679 #define CKLPS2 2
00680 #define CKLPS1 1
00681 #define CKLPS0 0
00682
00683
00684 #define OCIE0B 2
00685 #define OCIE0A 1
00686 #define TOIE0 0
00687
00688
00689 #define ICIE1 5
00690 #define OCIE1C 3
00691 #define OCIE1B 2
00692 #define OCIE1A 1
00693 #define TOIE1 0
00694
00695
00696 #define COM1A1 7
00697 #define COM1A0 6
00698 #define COM1B1 5
00699 #define COM1B0 4
00700 #define COM1C1 3
00701 #define COM1C0 2
00702 #define WGM11 1
00703 #define WGM10 0
00704
00705
00706 #define ICNC1 7
00707 #define ICES1 6
00708 #define WGM13 4
00709 #define WGM12 3
00710 #define CS12 2
00711 #define CS11 1
00712 #define CS10 0
00713
00714
00715 #define FOC1A 7
00716 #define FOC1B 6
00717 #define FOC1C 5
00718
00719
00720 #define RXC0 7
00721 #define TXC0 6
00722 #define UDRE0 5
00723 #define FE0 4
00724 #define DOR0 3
00725 #define UPE0 2
00726 #define U2X0 1
00727 #define MPCM0 0
00728
00729
00730 #define RXC1 7
00731 #define TXC1 6
00732 #define UDRE1 5
00733 #define FE1 4
00734 #define DOR1 3
00735 #define UPE1 2
00736 #define U2X1 1
00737 #define MPCM1 0
00738
00739
00740 #define RXCIE1 7
00741 #define TXCIE1 6
00742 #define UDRIE1 5
00743 #define RXEN1 4
00744 #define TXEN1 3
00745 #define UCSZ12 2
00746 #define RXB81 1
00747 #define TXB81 0
00748
00749
00750 #define UMSEL11 7
00751 #define UMSEL10 6
00752 #define UMSEL1 6 // for compatibility
00753 #define UPM11 5
00754 #define UPM10 4
00755 #define USBS1 3
00756 #define UCSZ11 2
00757 #define UCSZ10 1
00758 #define UCPOL1 0
00759
00760
00761 #define CTSEN 1
00762 #define RTSEN 0
00763
00764
00765 #define PCIE1 1
00766 #define PCIE0 0
00767
00768
00769 #define PCIF1 1
00770 #define PCIF0 0
00771
00772
00773
00774 #define DETACH 0 //
00775 #define RMWKUP 1 //
00776 #define RSTCPU 2 //
00777
00778
00779 #define SUSPI 0 //
00780
00781 #define SOFI 2 //
00782 #define EORSTI 3 //
00783 #define WAKEUPI 4 //
00784 #define EORSMI 5 //
00785 #define UPRSMI 6 //
00786
00787
00788 #define SUSPE 0 //
00789
00790 #define SOFE 2 //
00791 #define EORSTE 3 //
00792 #define WAKEUPE 4 //
00793 #define EORSME 5 //
00794 #define UPRSME 6 //
00795
00796
00797 #define UDADDR0 0 //
00798 #define UDADDR1 1 //
00799 #define UDADDR2 2 //
00800 #define UDADDR3 3 //
00801 #define UDADDR4 4 //
00802 #define UDADDR5 5 //
00803 #define UDADDR6 6 //
00804 #define ADDEN 7 //
00805
00806
00807 #define UDFNUML_0 0 //
00808 #define UDFNUML_1 1 //
00809 #define UDFNUML_2 2 //
00810 #define UDFNUML_3 3 //
00811 #define UDFNUML_4 4 //
00812 #define UDFNUML_5 5 //
00813 #define UDFNUML_6 6 //
00814 #define UDFNUML_7 7 //
00815
00816
00817 #define UDFNUMH_0 0 //
00818 #define UDFNUMH_1 1 //
00819 #define UDFNUMH_2 2 //
00820
00821
00822 #define FNCERR 4 //
00823
00824
00825 #define TXINI 0 //
00826 #define STALLEDI 1 //
00827 #define RXOUTI 2 //
00828 #define RXSTPI 3 //
00829 #define NAKOUTI 4 //
00830 #define RWAL 5 //
00831 #define NAKINI 6 //
00832 #define FIFOCON 7 //
00833
00834
00835 #define UENUM_0 0 //
00836 #define UENUM_1 1 //
00837 #define UENUM_2 2 //
00838
00839
00840 #define EPRST0 0 //
00841 #define EPRST1 1 //
00842 #define EPRST2 2 //
00843 #define EPRST3 3 //
00844 #define EPRST4 4 //
00845 #define EPRST5 5 //
00846 #define EPRST6 6 //
00847
00848
00849 #define EPEN 0 //
00850 #define RSTDT 3 //
00851 #define STALLRQC 4 //
00852 #define STALLRQ 5 //
00853
00854
00855 #define EPDIR 0 //
00856 #define NYETDIS 1 //
00857 #define AUTOSW 2 //
00858 #define ISOSW 3 //
00859 #define EPTYPE0 6 //
00860 #define EPTYPE1 7 //
00861
00862
00863 #define ALLOC 1 //
00864 #define EPBK0 2 //
00865 #define EPBK1 3 //
00866 #define EPSIZE0 4 //
00867 #define EPSIZE1 5 //
00868 #define EPSIZE2 6 //
00869
00870
00871 #define NBUSYBK0 0 //
00872 #define NBUSYBK1 1 //
00873 #define DTSEQ0 2 //
00874 #define DTSEQ1 3 //
00875 #define ZLPSEEN 4 //
00876 #define UNDERFI 5 //
00877 #define OVERFI 6 //
00878 #define CFGOK 7 //
00879
00880
00881 #define CURRBK0 0 //
00882 #define CURRBK1 1 //
00883 #define CTRLDIR 2 //
00884
00885
00886 #define TXINE 0 //
00887 #define STALLEDE 1 //
00888 #define RXOUTE 2 //
00889 #define RXSTPE 3 //
00890 #define NAKOUTE 4 //
00891 #define NAKINE 6 //
00892 #define FLERRE 7 //
00893
00894
00895 #define UEDATX_0 0 //
00896 #define UEDATX_1 1 //
00897 #define UEDATX_2 2 //
00898 #define UEDATX_3 3 //
00899 #define UEDATX_4 4 //
00900 #define UEDATX_5 5 //
00901 #define UEDATX_6 6 //
00902 #define UEDATX_7 7 //
00903
00904
00905 #define UEBCLX_0 0 //
00906 #define UEBCLX_1 1 //
00907 #define UEBCLX_2 2 //
00908 #define UEBCLX_3 3 //
00909 #define UEBCLX_4 4 //
00910 #define UEBCLX_5 5 //
00911 #define UEBCLX_6 6 //
00912 #define UEBCLX_7 7 //
00913
00914
00915 #define UEBCHX_0 0 //
00916 #define UEBCHX_1 1 //
00917 #define UEBCHX_2 2 //
00918
00919
00920 #define UEINT_0 0 //
00921 #define UEINT_1 1 //
00922 #define UEINT_2 2 //
00923 #define UEINT_3 3 //
00924 #define UEINT_4 4 //
00925 #define UEINT_5 5 //
00926 #define UEINT_6 6 //
00927
00928
00929
00930
00931
00932
00933
00934
00935 #define FRZCLK 5 //
00936
00937 #define USBE 7 //
00938
00939
00940
00941
00942
00943
00944
00945
00946
00947
00948
00949
00950
00951 #define PS2EN 0
00952
00953
00954 #define UPWE1 7
00955 #define UPWE0 6
00956 #define UPDRV1 5
00957 #define UPDRV0 4
00958 #define SCKI 3
00959 #define DATAI 2
00960 #define DPI 1
00961 #define DMI 0
00962
00963
00964
00965
00966
00967 #define RCSUT1 7
00968 #define RCSUT0 6
00969 #define EXSUT1 5
00970 #define EXSUT0 4
00971 #define RCE 3
00972 #define EXTE 2
00973 #define CLKS 0
00974
00975
00976 #define RCCKSEL3 7
00977 #define RCCKSEL2 6
00978 #define RCCKSEL1 5
00979 #define RCCKSEL0 4
00980 #define EXCKSEL3 3
00981 #define EXCKSEL2 2
00982 #define EXCKSEL1 1
00983 #define EXCKSEL0 0
00984
00985
00986 #define RCON 1
00987 #define EXTON 0
00988
00989
00990
00991
00992
00993 #define PLLP2 4
00994 #define PLLP1 3
00995 #define PLLP0 2
00996 #define PLLE 1
00997 #define PLOCK 0
00998
00999
01000
01001
01002
01003 #define REGDIS 0
01004
01005
01006
01007 #define XL r26
01008 #define XH r27
01009 #define YL r28
01010 #define YH r29
01011 #define ZL r30
01012 #define ZH r31
01013
01014
01015 #define PCINT6 6
01016 #define PCINT5 5
01017 #define PCINT4 4
01018 #define PCINT3 3
01019 #define PCINT2 2
01020 #define PCINT1 1
01021 #define PCINT0 0
01022
01023
01024 #define PCINT12 4
01025 #define PCINT11 3
01026 #define PCINT10 2
01027 #define PCINT9 1
01028 #define PCINT8 0
01029
01030 #endif
01031
01032
01033
01034
01035
01036
01037
01038
01039
01040
01041
01042
01043
01044