# Analog to Digital Convertor Peripheral

ADC (AT91S_ADC) 0xFFFD8000 (AT91C_BASE_ADC)

Periph ID AIC | Symbol | Description
4 | (AT91C_ID_ADC) | Analog-to-Digital Converter

Signal | Symbol | PIO controller | Description
ADTRG | (AT91C_PA8_ADTRG ) | PIOA Periph: B Bit: 8 | ADC External Trigger

Function | Description
AT91F_ADC_CfgPMC | Enable Peripheral clock in PMC for ADC
AT91F_ADC_CfgPIO | Configure PIO controllers to drive ADC signals

## ADC Software API (AT91S_ADC)

Offset | Field | Description
0x0 | ADC_CR | ADC Control Register
0x4 | ADC_MR | ADC Mode Register
0x10 | ADC_CHER ( ADC_CHER) | ADC Channel Enable Register
0x14 | ADC_CHDR ( ADC_CHDR) | ADC Channel Disable Register
0x18 | ADC_CHSR ( ADC_CHSR) | ADC Channel Status Register
0x1C | ADC_SR | ADC Status Register
0x20 | ADC_LCDR | ADC Last Converted Data Register
0x24 | ADC_IER | ADC Interrupt Enable Register
0x28 | ADC_IDR | ADC Interrupt Disable Register
0x2C | ADC_IMR | ADC Interrupt Mask Register
0x30 | ADC_CDR0 | ADC Channel Data Register 0
0x34 | ADC_CDR1 | ADC Channel Data Register 1
0x38 | ADC_CDR2 | ADC Channel Data Register 2
0x3C | ADC_CDR3 | ADC Channel Data Register 3
0x40 | ADC_CDR4 | ADC Channel Data Register 4
0x44 | ADC_CDR5 | ADC Channel Data Register 5
0x48 | ADC_CDR6 | ADC Channel Data Register 6
0x4C | ADC_CDR7 | ADC Channel Data Register 7
0x100 | ADC_RPR (PDC_RPR) | Receive Pointer Register
0x104 | ADC_RCR (PDC_RCR) | Receive Counter Register
0x108 | ADC_TPR (PDC_TPR) | Transmit Pointer Register
0x10C | ADC_TCR (PDC_TCR) | Transmit Counter Register
0x110 | ADC_RNPR (PDC_RNPR) | Receive Next Pointer Register
0x114 | ADC_RNCR (PDC_RNCR) | Receive Next Counter Register
0x118 | ADC_TNPR (PDC_TNPR) | Transmit Next Pointer Register
0x11C | ADC_TNCR (PDC_TNCR) | Transmit Next Counter Register
0x120 | ADC_PTCR (PDC_PTCR) | PDC Transfer Control Register
0x124 | ADC_PTSR (PDC_PTSR) | PDC Transfer Status Register

Function | Description
AT91F_ADC_GetConvertedDataCH0 | Return the Channel 0 Converted Data
AT91F_ADC_GetConvertedDataCH1 | Return the Channel 1 Converted Data
AT91F_ADC_GetConvertedDataCH2 | Return the Channel 2 Converted Data
AT91F_ADC_CfgModeReg | Configure the Mode Register of the ADC controller
AT91F_ADC_GetConvertedDataCH3 | Return the Channel 3 Converted Data
AT91F_ADC_GetConvertedDataCH4 | Return the Channel 4 Converted Data
AT91F_ADC_GetConvertedDataCH5 | Return the Channel 5 Converted Data
AT91F_ADC_GetConvertedDataCH6 | Return the Channel 6 Converted Data
AT91F_ADC_GetConvertedDataCH7 | Return the Channel 7 Converted Data
AT91F_ADC_GetChannelStatus | Return ADC Timer Register Value
AT91F_ADC_GetModeReg | Return the Mode Register of the ADC controller value
AT91F_ADC_DisableIt | Disable ADC interrupt
AT91F_ADC_StartConversion | Software request for a analog to digital conversion
AT91F_ADC_GetStatus | Return ADC Interrupt Status
AT91F_ADC_GetLastConvertedData | Return the Last Converted Data
AT91F_ADC_SoftReset | Software reset
AT91F_ADC_CfgTimings | Configure the different necessary timings of the ADC controller
AT91F_ADC_DisableChannel | Return ADC Timer Register Value
AT91F_ADC_EnableIt | Enable ADC interrupt
AT91F_ADC_GetInterruptMaskStatus | Return ADC Interrupt Mask Status
AT91F_ADC_IsStatusSet | Test if ADC Status is Set
AT91F_ADC_EnableChannel | Return ADC Timer Register Value
AT91F_ADC_IsInterruptMasked | Test if ADC Interrupt is Masked

## ADC Register Description

#### ADC: AT91_REG ADC_CR ADC Control Register

- ADC AT91C_ADC_CR 0xFFFD8000

Offset | Name | Description
0 | ADC_SWRST AT91C_ADC_SWRST | Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset.
1 | ADC_START AT91C_ADC_START | Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion and clears all EOC bits.

#### ADC: AT91_REG ADC_MR ADC Mode Register

- ADC AT91C_ADC_MR 0xFFFD8004

Offset | Name | Description
0 | ADC_TRGEN AT91C_ADC_TRGEN | Trigger Enable Value | Label | Description
0 | ADC_TRGEN_DIS AT91C_ADC_TRGEN_DIS | Hradware triggers are disabled. Starting a conversion is only possible by software
1 | ADC_TRGEN_EN AT91C_ADC_TRGEN_EN | Hardware trigger selected by TRGSEL field is enabled.
3..1 | ADC_TRGSEL AT91C_ADC_TRGSEL | Trigger Selection Value | Label | Description
0 | ADC_TRGSEL_TIOA0 AT91C_ADC_TRGSEL_TIOA0 | Selected TRGSEL = TIAO0
1 | ADC_TRGSEL_TIOA1 AT91C_ADC_TRGSEL_TIOA1 | Selected TRGSEL = TIAO1
2 | ADC_TRGSEL_TIOA2 AT91C_ADC_TRGSEL_TIOA2 | Selected TRGSEL = TIAO2
3 | ADC_TRGSEL_TIOA3 AT91C_ADC_TRGSEL_TIOA3 | Selected TRGSEL = TIAO3
4 | ADC_TRGSEL_TIOA4 AT91C_ADC_TRGSEL_TIOA4 | Selected TRGSEL = TIAO4
5 | ADC_TRGSEL_TIOA5 AT91C_ADC_TRGSEL_TIOA5 | Selected TRGSEL = TIAO5
6 | ADC_TRGSEL_EXT AT91C_ADC_TRGSEL_EXT | Selected TRGSEL = External Trigger
4 | ADC_LOWRES AT91C_ADC_LOWRES | Resolution. Value | Label | Description
0 | ADC_LOWRES_10_BIT AT91C_ADC_LOWRES_10_BIT | 10-bit resolution
1 | ADC_LOWRES_8_BIT AT91C_ADC_LOWRES_8_BIT | 8-bit resolution
5 | ADC_SLEEP AT91C_ADC_SLEEP | Sleep Mode Value | Label | Description
0 | ADC_SLEEP_NORMAL_MODE AT91C_ADC_SLEEP_NORMAL_MODE | Normal Mode
1 | ADC_SLEEP_MODE AT91C_ADC_SLEEP_MODE | Sleep Mode
13..8 | ADC_PRESCAL AT91C_ADC_PRESCAL | Prescaler rate selection This field defines the conversion clock in function of the Master Clcok (MCK). ADCClock = MCK/((PRESCAL + 1) x 2). Range = MCK/2 to MCK/128.
20..16 | ADC_STARTUP AT91C_ADC_STARTUP | Startup Time This field defines the necessary startup time in function of the ADC Clock. Startup Time = (STARTUP+1)* 8 / ADCClock.
27..24 | ADC_SHTIM AT91C_ADC_SHTIM | Sample & Hold Time This field defines the necessary time between 2 channels selection to guarantee the converted value in function of the ADC Clock. Sample & Hold Time = (SHTIM+1) / ADCClock.

#### ADC: AT91_REG ADC_CHER ADC Channel Enable Register

- ADC AT91C_ADC_CHER 0xFFFD8010

0 = No effect.
1 = Enable the corresponding channel

Offset | Name | Description
0 | ADC_CH0 AT91C_ADC_CH0 | Channel 0
1 | ADC_CH1 AT91C_ADC_CH1 | Channel 1
2 | ADC_CH2 AT91C_ADC_CH2 | Channel 2
3 | ADC_CH3 AT91C_ADC_CH3 | Channel 3
4 | ADC_CH4 AT91C_ADC_CH4 | Channel 4
5 | ADC_CH5 AT91C_ADC_CH5 | Channel 5
6 | ADC_CH6 AT91C_ADC_CH6 | Channel 6
7 | ADC_CH7 AT91C_ADC_CH7 | Channel 7

#### ADC: AT91_REG ADC_CHDR ADC Channel Disable Register

- ADC AT91C_ADC_CHDR 0xFFFD8014

0 = No effect.
1 = Disable the corresponding channel

Offset | Name | Description
0 | ADC_CH0 AT91C_ADC_CH0 | Channel 0
1 | ADC_CH1 AT91C_ADC_CH1 | Channel 1
2 | ADC_CH2 AT91C_ADC_CH2 | Channel 2
3 | ADC_CH3 AT91C_ADC_CH3 | Channel 3
4 | ADC_CH4 AT91C_ADC_CH4 | Channel 4
5 | ADC_CH5 AT91C_ADC_CH5 | Channel 5
6 | ADC_CH6 AT91C_ADC_CH6 | Channel 6
7 | ADC_CH7 AT91C_ADC_CH7 | Channel 7

#### ADC: AT91_REG ADC_CHSR ADC Channel Status Register

- ADC AT91C_ADC_CHSR 0xFFFD8018

0 = Corresponding channel is disabled.
1 = Corresponding channel is enabled

Offset | Name | Description
0 | ADC_CH0 AT91C_ADC_CH0 | Channel 0
1 | ADC_CH1 AT91C_ADC_CH1 | Channel 1
2 | ADC_CH2 AT91C_ADC_CH2 | Channel 2
3 | ADC_CH3 AT91C_ADC_CH3 | Channel 3
4 | ADC_CH4 AT91C_ADC_CH4 | Channel 4
5 | ADC_CH5 AT91C_ADC_CH5 | Channel 5
6 | ADC_CH6 AT91C_ADC_CH6 | Channel 6
7 | ADC_CH7 AT91C_ADC_CH7 | Channel 7

#### ADC: AT91_REG ADC_SR ADC Status Register

- ADC AT91C_ADC_SR 0xFFFD801C

EOCx:
0 = Channel x is disabled, or the conversion is not finished.
1 = Channel x is enabled and conversion is complete.
OVREx:
0 = No overrun on the channel x since the last read of ADC_SR.
1 = There has been an overrun on the channel x since the last read of ADC_SR.
DRDY:
0 = No data has been converted since the last read of ADC_LCDR.
1 = At least one data has been converted since the last read of ADC_LCDR.
GOVRE:
0 = No Overrun Error occured since the last read of ADC_LCDR.
1 = At least one Overrun Error has occured since the last read of ADC_LCDR.
ENDBUF:
0 = The PDC does not report an end of buffer.
1 = The PDC reports an end of buffer.
BUFFULL:
0 = The PDC does not report a buffer full.
1 = The PDC reports a buffer full.

Offset | Name | Description
0 | ADC_EOC0 AT91C_ADC_EOC0 | End of Conversion
1 | ADC_EOC1 AT91C_ADC_EOC1 | End of Conversion
2 | ADC_EOC2 AT91C_ADC_EOC2 | End of Conversion
3 | ADC_EOC3 AT91C_ADC_EOC3 | End of Conversion
4 | ADC_EOC4 AT91C_ADC_EOC4 | End of Conversion
5 | ADC_EOC5 AT91C_ADC_EOC5 | End of Conversion
6 | ADC_EOC6 AT91C_ADC_EOC6 | End of Conversion
7 | ADC_EOC7 AT91C_ADC_EOC7 | End of Conversion
8 | ADC_OVRE0 AT91C_ADC_OVRE0 | Overrun Error
9 | ADC_OVRE1 AT91C_ADC_OVRE1 | Overrun Error
10 | ADC_OVRE2 AT91C_ADC_OVRE2 | Overrun Error
11 | ADC_OVRE3 AT91C_ADC_OVRE3 | Overrun Error
12 | ADC_OVRE4 AT91C_ADC_OVRE4 | Overrun Error
13 | ADC_OVRE5 AT91C_ADC_OVRE5 | Overrun Error
14 | ADC_OVRE6 AT91C_ADC_OVRE6 | Overrun Error
15 | ADC_OVRE7 AT91C_ADC_OVRE7 | Overrun Error
16 | ADC_DRDY AT91C_ADC_DRDY | Data Ready
17 | ADC_GOVRE AT91C_ADC_GOVRE | General Overrun
18 | ADC_ENDRX AT91C_ADC_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
19 | ADC_RXBUFF AT91C_ADC_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full.

#### ADC: AT91_REG ADC_LCDR ADC Last Converted Data Register

- ADC AT91C_ADC_LCDR 0xFFFD8020

Offset | Name | Description
9..0 | ADC_LDATA AT91C_ADC_LDATA | Last Data Converted Data converted is placed at the end of conversion and remains until a new one is completed.

#### ADC: AT91_REG ADC_IER ADC Interrupt Enable Register

- ADC AT91C_ADC_IER 0xFFFD8024

0 = No effect. 1 = Enables the corresponding interrupt.

Offset | Name | Description
0 | ADC_EOC0 AT91C_ADC_EOC0 | End of Conversion
1 | ADC_EOC1 AT91C_ADC_EOC1 | End of Conversion
2 | ADC_EOC2 AT91C_ADC_EOC2 | End of Conversion
3 | ADC_EOC3 AT91C_ADC_EOC3 | End of Conversion
4 | ADC_EOC4 AT91C_ADC_EOC4 | End of Conversion
5 | ADC_EOC5 AT91C_ADC_EOC5 | End of Conversion
6 | ADC_EOC6 AT91C_ADC_EOC6 | End of Conversion
7 | ADC_EOC7 AT91C_ADC_EOC7 | End of Conversion
8 | ADC_OVRE0 AT91C_ADC_OVRE0 | Overrun Error
9 | ADC_OVRE1 AT91C_ADC_OVRE1 | Overrun Error
10 | ADC_OVRE2 AT91C_ADC_OVRE2 | Overrun Error
11 | ADC_OVRE3 AT91C_ADC_OVRE3 | Overrun Error
12 | ADC_OVRE4 AT91C_ADC_OVRE4 | Overrun Error
13 | ADC_OVRE5 AT91C_ADC_OVRE5 | Overrun Error
14 | ADC_OVRE6 AT91C_ADC_OVRE6 | Overrun Error
15 | ADC_OVRE7 AT91C_ADC_OVRE7 | Overrun Error
16 | ADC_DRDY AT91C_ADC_DRDY | Data Ready
17 | ADC_GOVRE AT91C_ADC_GOVRE | General Overrun
18 | ADC_ENDRX AT91C_ADC_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
19 | ADC_RXBUFF AT91C_ADC_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full.

#### ADC: AT91_REG ADC_IDR ADC Interrupt Disable Register

- ADC AT91C_ADC_IDR 0xFFFD8028

0 = No effect. 1 = disables the corresponding interrupt.

Offset | Name | Description
0 | ADC_EOC0 AT91C_ADC_EOC0 | End of Conversion
1 | ADC_EOC1 AT91C_ADC_EOC1 | End of Conversion
2 | ADC_EOC2 AT91C_ADC_EOC2 | End of Conversion
3 | ADC_EOC3 AT91C_ADC_EOC3 | End of Conversion
4 | ADC_EOC4 AT91C_ADC_EOC4 | End of Conversion
5 | ADC_EOC5 AT91C_ADC_EOC5 | End of Conversion
6 | ADC_EOC6 AT91C_ADC_EOC6 | End of Conversion
7 | ADC_EOC7 AT91C_ADC_EOC7 | End of Conversion
8 | ADC_OVRE0 AT91C_ADC_OVRE0 | Overrun Error
9 | ADC_OVRE1 AT91C_ADC_OVRE1 | Overrun Error
10 | ADC_OVRE2 AT91C_ADC_OVRE2 | Overrun Error
11 | ADC_OVRE3 AT91C_ADC_OVRE3 | Overrun Error
12 | ADC_OVRE4 AT91C_ADC_OVRE4 | Overrun Error
13 | ADC_OVRE5 AT91C_ADC_OVRE5 | Overrun Error
14 | ADC_OVRE6 AT91C_ADC_OVRE6 | Overrun Error
15 | ADC_OVRE7 AT91C_ADC_OVRE7 | Overrun Error
16 | ADC_DRDY AT91C_ADC_DRDY | Data Ready
17 | ADC_GOVRE AT91C_ADC_GOVRE | General Overrun
18 | ADC_ENDRX AT91C_ADC_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
19 | ADC_RXBUFF AT91C_ADC_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full.

#### ADC: AT91_REG ADC_IMR ADC Interrupt Mask Register

- ADC AT91C_ADC_IMR 0xFFFD802C

0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.

Offset | Name | Description
0 | ADC_EOC0 AT91C_ADC_EOC0 | End of Conversion
1 | ADC_EOC1 AT91C_ADC_EOC1 | End of Conversion
2 | ADC_EOC2 AT91C_ADC_EOC2 | End of Conversion
3 | ADC_EOC3 AT91C_ADC_EOC3 | End of Conversion
4 | ADC_EOC4 AT91C_ADC_EOC4 | End of Conversion
5 | ADC_EOC5 AT91C_ADC_EOC5 | End of Conversion
6 | ADC_EOC6 AT91C_ADC_EOC6 | End of Conversion
7 | ADC_EOC7 AT91C_ADC_EOC7 | End of Conversion
8 | ADC_OVRE0 AT91C_ADC_OVRE0 | Overrun Error
9 | ADC_OVRE1 AT91C_ADC_OVRE1 | Overrun Error
10 | ADC_OVRE2 AT91C_ADC_OVRE2 | Overrun Error
11 | ADC_OVRE3 AT91C_ADC_OVRE3 | Overrun Error
12 | ADC_OVRE4 AT91C_ADC_OVRE4 | Overrun Error
13 | ADC_OVRE5 AT91C_ADC_OVRE5 | Overrun Error
14 | ADC_OVRE6 AT91C_ADC_OVRE6 | Overrun Error
15 | ADC_OVRE7 AT91C_ADC_OVRE7 | Overrun Error
16 | ADC_DRDY AT91C_ADC_DRDY | Data Ready
17 | ADC_GOVRE AT91C_ADC_GOVRE | General Overrun
18 | ADC_ENDRX AT91C_ADC_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
19 | ADC_RXBUFF AT91C_ADC_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full.

#### ADC: AT91_REG ADC_CDR0 ADC Channel Data Register 0

- ADC AT91C_ADC_CDR0 0xFFFD8030

Offset | Name | Description
9..0 | ADC_DATA AT91C_ADC_DATA | Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

#### ADC: AT91_REG ADC_CDR1 ADC Channel Data Register 1

- ADC AT91C_ADC_CDR1 0xFFFD8034

Offset | Name | Description
9..0 | ADC_DATA AT91C_ADC_DATA | Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

#### ADC: AT91_REG ADC_CDR2 ADC Channel Data Register 2

- ADC AT91C_ADC_CDR2 0xFFFD8038

Offset | Name | Description
9..0 | ADC_DATA AT91C_ADC_DATA | Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

#### ADC: AT91_REG ADC_CDR3 ADC Channel Data Register 3

- ADC AT91C_ADC_CDR3 0xFFFD803C

Offset | Name | Description
9..0 | ADC_DATA AT91C_ADC_DATA | Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

#### ADC: AT91_REG ADC_CDR4 ADC Channel Data Register 4

- ADC AT91C_ADC_CDR4 0xFFFD8040

Offset | Name | Description
9..0 | ADC_DATA AT91C_ADC_DATA | Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

#### ADC: AT91_REG ADC_CDR5 ADC Channel Data Register 5

- ADC AT91C_ADC_CDR5 0xFFFD8044

Offset | Name | Description
9..0 | ADC_DATA AT91C_ADC_DATA | Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

#### ADC: AT91_REG ADC_CDR6 ADC Channel Data Register 6

- ADC AT91C_ADC_CDR6 0xFFFD8048

Offset | Name | Description
9..0 | ADC_DATA AT91C_ADC_DATA | Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

#### ADC: AT91_REG ADC_CDR7 ADC Channel Data Register 7

- ADC AT91C_ADC_CDR7 0xFFFD804C

Offset | Name | Description
9..0 | ADC_DATA AT91C_ADC_DATA | Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

#### ADC: AT91S_PDC ADC_PDC PDC interface

- ADC AT91C_ADC_ADC 0xFFFD8100