# Serial Parallel Interface Peripheral

SPI (AT91S_SPI) 0xFFFE0000 (AT91C_BASE_SPI)

Periph ID AIC | Symbol | Description
5 | (AT91C_ID_SPI) | Serial Peripheral Interface

Signal | Symbol | PIO controller | Description
NPCS0 | (AT91C_PA11_NPCS0 ) | PIOA Periph: A Bit: 11 | SPI Peripheral Chip Select 0
MOSI | (AT91C_PA13_MOSI ) | PIOA Periph: A Bit: 13 | SPI Master Out Slave
NPCS1 | (AT91C_PA31_NPCS1 ) | PIOA Periph: A Bit: 31 | SPI Peripheral Chip Select 1
NPCS1 | (AT91C_PA9_NPCS1 ) | PIOA Periph: B Bit: 9 | SPI Peripheral Chip Select 1
NPCS2 | (AT91C_PA30_NPCS2 ) | PIOA Periph: B Bit: 30 | SPI Peripheral Chip Select 2
NPCS2 | (AT91C_PA10_NPCS2 ) | PIOA Periph: B Bit: 10 | SPI Peripheral Chip Select 2
NPCS3 | (AT91C_PA22_NPCS3 ) | PIOA Periph: B Bit: 22 | SPI Peripheral Chip Select 3
NPCS3 | (AT91C_PA3_NPCS3 ) | PIOA Periph: B Bit: 3 | SPI Peripheral Chip Select 3
NPCS3 | (AT91C_PA5_NPCS3 ) | PIOA Periph: B Bit: 5 | SPI Peripheral Chip Select 3
MISO | (AT91C_PA12_MISO ) | PIOA Periph: A Bit: 12 | SPI Master In Slave
SPCK | (AT91C_PA14_SPCK ) | PIOA Periph: A Bit: 14 | SPI Serial Clock

Function | Description
AT91F_SPI_CfgPMC | Enable Peripheral clock in PMC for SPI
AT91F_SPI_CfgPIO | Configure PIO controllers to drive SPI signals

## SPI Software API (AT91S_SPI)

Offset | Field | Description
0x0 | SPI_CR | Control Register
0x4 | SPI_MR | Mode Register
0x8 | SPI_RDR | Receive Data Register
0xC | SPI_TDR | Transmit Data Register
0x10 | SPI_SR | Status Register
0x14 | SPI_IER | Interrupt Enable Register
0x18 | SPI_IDR | Interrupt Disable Register
0x1C | SPI_IMR | Interrupt Mask Register
0x30 | SPI_CSR[4] (SPI_CSR) | Chip Select Register
0x100 | SPI_RPR (PDC_RPR) | Receive Pointer Register
0x104 | SPI_RCR (PDC_RCR) | Receive Counter Register
0x108 | SPI_TPR (PDC_TPR) | Transmit Pointer Register
0x10C | SPI_TCR (PDC_TCR) | Transmit Counter Register
0x110 | SPI_RNPR (PDC_RNPR) | Receive Next Pointer Register
0x114 | SPI_RNCR (PDC_RNCR) | Receive Next Counter Register
0x118 | SPI_TNPR (PDC_TNPR) | Transmit Next Pointer Register
0x11C | SPI_TNCR (PDC_TNCR) | Transmit Next Counter Register
0x120 | SPI_PTCR (PDC_PTCR) | PDC Transfer Control Register
0x124 | SPI_PTSR (PDC_PTSR) | PDC Transfer Status Register

Function | Description
AT91F_SPI_Reset | Reset the SPI controller
AT91F_SPI_Close | Close SPI: disable IT disable transfert, close PDC
AT91F_SPI_Disable | Disable the SPI controller
AT91F_SPI_Enable | Enable the SPI controller
AT91F_SPI_SendFrame | Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
AT91F_SPI_CfgMode | Enable the SPI controller
AT91F_SPI_GetChar | Receive a character,does not check if a character is available
AT91F_SPI_PutChar | Send a character,does not check if ready to send
AT91F_SPI_DisableIt | Disable SPI interrupt
AT91F_SPI_GetInterruptMaskStatus | Return SPI Interrupt Mask Status
AT91F_SPI_IsInterruptMasked | Test if SPI Interrupt is Masked
AT91F_SPI_ReceiveFrame | Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
AT91F_SPI_Open | Open a SPI Port
AT91F_SPI_CfgCs | Configure SPI chip select register
AT91F_SPI_EnableIt | Enable SPI interrupt
AT91F_SPI_CfgPCS | Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected

## SPI Register Description

#### SPI: AT91_REG SPI_CR Control Register

- SPI AT91C_SPI_CR 0xFFFE0000

Offset | Name | Description
0 | SPI_SPIEN AT91C_SPI_SPIEN | SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data.
1 | SPI_SPIDIS AT91C_SPI_SPIDIS | SPI Disable 0 = No effect. 1 = Disables the SPI. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.
7 | SPI_SWRST AT91C_SPI_SWRST | SPI Software reset 0 = No effect. 1 = Resets the SPI. A software triggered hardware reset of the SPI interface is performed.
24 | SPI_LASTXFER AT91C_SPI_LASTXFER | SPI Last Transfer 0 = No effect. 1 = Deassert the NPCS after all transfers occured. Useful when CSAAT is set.

#### SPI: AT91_REG SPI_MR Mode Register

- SPI AT91C_SPI_MR 0xFFFE0004

Offset | Name | Description
0 | SPI_MSTR AT91C_SPI_MSTR | Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode.
1 | SPI_PS AT91C_SPI_PS | Peripheral Select Value | Label | Description
0 | SPI_PS_FIXED AT91C_SPI_PS_FIXED | Fixed Peripheral Select
1 | SPI_PS_VARIABLE AT91C_SPI_PS_VARIABLE | Variable Peripheral Select
2 | SPI_PCSDEC AT91C_SPI_PCSDEC | Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 16 Chip Select signals can be generated with the four lines using an external 4- to 16- bit decoder. The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 15 (1) . Note: 1. The 16th state corresponds to a state in which all chip selects are inactive. This allows a different clock configuration to be defined by each chip select register.
3 | SPI_FDIV AT91C_SPI_FDIV | Clock Selection 0 = SPI Master Clock equals MCK 1 = SPI Master Clock equals MCK/N. Product dependancy
4 | SPI_MODFDIS AT91C_SPI_MODFDIS | Mode Fault Detection 0 = Mode Fault Detection is enabled 1 = Mode Fault Detection is disabled
7 | SPI_LLB AT91C_SPI_LLB | Clock Selection 0 = Local loopback path disabled 1 = Local loopback path enabled LLB controls the local loopback on the data serializer for testing in master mode only.
19..16 | SPI_PCS AT91C_SPI_PCS | Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC=0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC=1: NPCS[3:0] output signals = PCS
31..24 | SPI_DLYBCS AT91C_SPI_DLYBCS | Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six SPI Master Clock periods will be inserted by default. Otherwise, the following equation determines the delay: Delay_ Between_Chip_Selects = DLYBCS * SPI_Master_Clock_period

#### SPI: AT91_REG SPI_RDR Receive Data Register

- SPI AT91C_SPI_RDR 0xFFFE0008

Offset | Name | Description
15..0 | SPI_RD AT91C_SPI_RD | Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
19..16 | SPI_RPCS AT91C_SPI_RPCS | Peripheral Chip Select Status In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero.

#### SPI: AT91_REG SPI_TDR Transmit Data Register

- SPI AT91C_SPI_TDR 0xFFFE000C

Offset | Name | Description
15..0 | SPI_TD AT91C_SPI_TD | Transmit Data Data which is to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be writ-ten to the transmit data register in a right-justified format.
19..16 | SPI_TPCS AT91C_SPI_TPCS | Peripheral Chip Select Status This field is only used if Variable Peripheral Select is active (PS = 1) and if the SPI is in Master Mode. If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS
24 | SPI_LASTXFER AT91C_SPI_LASTXFER | SPI Last Transfer 0 = No effect. 1 = Deassert the NPCS after all transfers occured. Useful when CSAAT is set.

#### SPI: AT91_REG SPI_SR Status Register

- SPI AT91C_SPI_SR 0xFFFE0010

Offset | Name | Description
0 | SPI_RDRF AT91C_SPI_RDRF | Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1= Data has been received and the received data has been transferred from the serializer to SPI_RDR since the lastread of SPI_RDR.
1 | SPI_TDRE AT91C_SPI_TDRE | Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred in the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
2 | SPI_MODF AT91C_SPI_MODF | Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR.
3 | SPI_OVRES AT91C_SPI_OVRES | Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
4 | SPI_ENDRX AT91C_SPI_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
5 | SPI_ENDTX AT91C_SPI_ENDTX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.
6 | SPI_RXBUFF AT91C_SPI_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full.
7 | SPI_TXBUFE AT91C_SPI_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty
8 | SPI_NSSR AT91C_SPI_NSSR | NSSR Interrupt 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occured on NSS pin since last read.
9 | SPI_TXEMPTY AT91C_SPI_TXEMPTY | TXEMPTY Interrupt As soon as a data is written in the SPI_TDR. The SPI_TDR register and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.
16 | SPI_SPIENS AT91C_SPI_SPIENS | Enable Status 0 = SPI is disabled. 1 = SPI is enabled.

#### SPI: AT91_REG SPI_IER Interrupt Enable Register

- SPI AT91C_SPI_IER 0xFFFE0014

Offset | Name | Description
0 | SPI_RDRF AT91C_SPI_RDRF | Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1= Data has been received and the received data has been transferred from the serializer to SPI_RDR since the lastread of SPI_RDR.
1 | SPI_TDRE AT91C_SPI_TDRE | Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred in the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
2 | SPI_MODF AT91C_SPI_MODF | Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR.
3 | SPI_OVRES AT91C_SPI_OVRES | Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
4 | SPI_ENDRX AT91C_SPI_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
5 | SPI_ENDTX AT91C_SPI_ENDTX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.
6 | SPI_RXBUFF AT91C_SPI_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full.
7 | SPI_TXBUFE AT91C_SPI_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty
8 | SPI_NSSR AT91C_SPI_NSSR | NSSR Interrupt 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occured on NSS pin since last read.
9 | SPI_TXEMPTY AT91C_SPI_TXEMPTY | TXEMPTY Interrupt As soon as a data is written in the SPI_TDR. The SPI_TDR register and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.

#### SPI: AT91_REG SPI_IDR Interrupt Disable Register

- SPI AT91C_SPI_IDR 0xFFFE0018

Offset | Name | Description
0 | SPI_RDRF AT91C_SPI_RDRF | Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1= Data has been received and the received data has been transferred from the serializer to SPI_RDR since the lastread of SPI_RDR.
1 | SPI_TDRE AT91C_SPI_TDRE | Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred in the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
2 | SPI_MODF AT91C_SPI_MODF | Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR.
3 | SPI_OVRES AT91C_SPI_OVRES | Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
4 | SPI_ENDRX AT91C_SPI_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
5 | SPI_ENDTX AT91C_SPI_ENDTX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.
6 | SPI_RXBUFF AT91C_SPI_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full.
7 | SPI_TXBUFE AT91C_SPI_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty
8 | SPI_NSSR AT91C_SPI_NSSR | NSSR Interrupt 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occured on NSS pin since last read.
9 | SPI_TXEMPTY AT91C_SPI_TXEMPTY | TXEMPTY Interrupt As soon as a data is written in the SPI_TDR. The SPI_TDR register and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.

#### SPI: AT91_REG SPI_IMR Interrupt Mask Register

- SPI AT91C_SPI_IMR 0xFFFE001C

Offset | Name | Description
0 | SPI_RDRF AT91C_SPI_RDRF | Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1= Data has been received and the received data has been transferred from the serializer to SPI_RDR since the lastread of SPI_RDR.
1 | SPI_TDRE AT91C_SPI_TDRE | Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred in the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
2 | SPI_MODF AT91C_SPI_MODF | Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR.
3 | SPI_OVRES AT91C_SPI_OVRES | Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
4 | SPI_ENDRX AT91C_SPI_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
5 | SPI_ENDTX AT91C_SPI_ENDTX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.
6 | SPI_RXBUFF AT91C_SPI_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full.
7 | SPI_TXBUFE AT91C_SPI_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty
8 | SPI_NSSR AT91C_SPI_NSSR | NSSR Interrupt 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occured on NSS pin since last read.
9 | SPI_TXEMPTY AT91C_SPI_TXEMPTY | TXEMPTY Interrupt As soon as a data is written in the SPI_TDR. The SPI_TDR register and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.

#### SPI: AT91_REG SPI_CSR Chip Select Register

- SPI AT91C_SPI_CSR 0xFFFE0030

Offset | Name | Description
0 | SPI_CPOL AT91C_SPI_CPOL | Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce a desired clock/data relationship between master and slave devices.
1 | SPI_NCPHA AT91C_SPI_NCPHA | Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce a desired clock/data relationship between master and slave devices.
2 | SPI_CSAAT AT91C_SPI_CSAAT | Chip Select Active After Transfer 0 = The PCS Line raises at soon as the last transfer is achieved. 1 = The PCS does not raise after the last transfer is acheived. It remains active until a new transfer is requested on a different chip select.
7..4 | SPI_BITS AT91C_SPI_BITS | Bits Per Transfer The BITS field determines the number of data bits transferred. Value | Label | Description
0 | SPI_BITS_8 AT91C_SPI_BITS_8 | 8 Bits Per transfer
1 | SPI_BITS_9 AT91C_SPI_BITS_9 | 9 Bits Per transfer
2 | SPI_BITS_10 AT91C_SPI_BITS_10 | 10 Bits Per transfer
3 | SPI_BITS_11 AT91C_SPI_BITS_11 | 11 Bits Per transfer
4 | SPI_BITS_12 AT91C_SPI_BITS_12 | 12 Bits Per transfer
5 | SPI_BITS_13 AT91C_SPI_BITS_13 | 13 Bits Per transfer
6 | SPI_BITS_14 AT91C_SPI_BITS_14 | 14 Bits Per transfer
7 | SPI_BITS_15 AT91C_SPI_BITS_15 | 15 Bits Per transfer
8 | SPI_BITS_16 AT91C_SPI_BITS_16 | 16 Bits Per transfer
15..8 | SPI_SCBR AT91C_SPI_SCBR | Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the SPI Master Clock(selected between MCK and MCK/32). The baud rate is selected by writing a value from 2 to 255 in the field SCBR. The following equation determines the SPCK baud rate: SPCK_Baud_Rate = SPI_Master_Clock_frequency / (2 x SCBR) Giving SCBR a value of zero or one disables the baud rate generator. SPCK is disabled and assumes its inactive state value. No serial transfers may occur. At reset, baud rate is disabled.
23..16 | SPI_DLYBS AT91C_SPI_DLYBS | Serial Clock Baud Rate This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equation determines the delay: NPCS_to_SPCK_Delay = DLYBS * SPI_Master_Clock_period
31..24 | SPI_DLYBCT AT91C_SPI_DLYBCT | Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, a delay of four SPI Master Clock periods are inserted. Otherwise, the following equation determines the delay: Delay_After_Transfer = 32 * DLYBCT * SPI_Master_Clock_period

#### SPI: AT91S_PDC SPI_PDC PDC interface

- SPI AT91C_SPI_SPI 0xFFFE0100