# PWMC Channel Interface Peripheral

PWMC_CH3 (AT91S_PWMC_CH) 0xFFFCC260 (AT91C_BASE_PWMC_CH3)

Signal | Symbol | PIO controller | Description
PWM3 | (AT91C_PA14_PWM3 ) | PIOA Periph: B Bit: 14 | PWM Channel 3
PWM3 | (AT91C_PA7_PWM3 ) | PIOA Periph: B Bit: 7 | PWM Channel 3

Function | Description
AT91F_PWMC_CH3_CfgPIO | Configure PIO controllers to drive PWMC_CH3 signals

PWMC_CH2 (AT91S_PWMC_CH) 0xFFFCC240 (AT91C_BASE_PWMC_CH2)

Signal | Symbol | PIO controller | Description
PWM2 | (AT91C_PA25_PWM2 ) | PIOA Periph: B Bit: 25 | PWM Channel 2
PWM2 | (AT91C_PA2_PWM2 ) | PIOA Periph: A Bit: 2 | PWM Channel 2
PWM2 | (AT91C_PA13_PWM2 ) | PIOA Periph: B Bit: 13 | PWM Channel 2

Function | Description
AT91F_PWMC_CH2_CfgPIO | Configure PIO controllers to drive PWMC_CH2 signals

PWMC_CH1 (AT91S_PWMC_CH) 0xFFFCC220 (AT91C_BASE_PWMC_CH1)

Signal | Symbol | PIO controller | Description
PWM1 | (AT91C_PA24_PWM1 ) | PIOA Periph: B Bit: 24 | PWM Channel 1
PWM1 | (AT91C_PA1_PWM1 ) | PIOA Periph: A Bit: 1 | PWM Channel 1
PWM1 | (AT91C_PA12_PWM1 ) | PIOA Periph: B Bit: 12 | PWM Channel 1

Function | Description
AT91F_PWMC_CH1_CfgPIO | Configure PIO controllers to drive PWMC_CH1 signals

PWMC_CH0 (AT91S_PWMC_CH) 0xFFFCC200 (AT91C_BASE_PWMC_CH0)

Signal | Symbol | PIO controller | Description
PWM0 | (AT91C_PA23_PWM0 ) | PIOA Periph: B Bit: 23 | PWM Channel 0
PWM0 | (AT91C_PA0_PWM0 ) | PIOA Periph: A Bit: 0 | PWM Channel 0
PWM0 | (AT91C_PA11_PWM0 ) | PIOA Periph: B Bit: 11 | PWM Channel 0

Function | Description
AT91F_PWMC_CH0_CfgPIO | Configure PIO controllers to drive PWMC_CH0 signals

## PWMC_CH Software API (AT91S_PWMC_CH)

Offset | Field | Description
0x0 | PWMC_CMR | Channel Mode Register
0x4 | PWMC_CDTYR | Channel Duty Cycle Register
0x8 | PWMC_CPRDR | Channel Period Register
0xC | PWMC_CCNTR | Channel Counter Register
0x10 | PWMC_CUPDR | Channel Update Register
0x14 | PWMC_Reserved[3] (PWMC_RESERVED) | Reserved

## PWMC_CH Register Description

#### PWMC_CH: AT91_REG PWMC_CMR Channel Mode Register

- PWMC_CH3 AT91C_CH3_CMR 0xFFFCC260
- PWMC_CH2 AT91C_CH2_CMR 0xFFFCC240
- PWMC_CH1 AT91C_CH1_CMR 0xFFFCC220
- PWMC_CH0 AT91C_CH0_CMR 0xFFFCC200

Offset | Name | Description
3..0 | PWMC_CPRE AT91C_PWMC_CPRE | Channel Pre-scaler : PWMC_CLKx Value | Label | Description
0 | PWMC_CPRE_MCK AT91C_PWMC_CPRE_MCK |
1 | PWMC_CPRE_MCK/2 AT91C_PWMC_CPRE_MCK/2 |
2 | PWMC_CPRE_MCK/4 AT91C_PWMC_CPRE_MCK/4 |
3 | PWMC_CPRE_MCK/8 AT91C_PWMC_CPRE_MCK/8 |
4 | PWMC_CPRE_MCK/16 AT91C_PWMC_CPRE_MCK/16 |
5 | PWMC_CPRE_MCK/32 AT91C_PWMC_CPRE_MCK/32 |
6 | PWMC_CPRE_MCK/64 AT91C_PWMC_CPRE_MCK/64 |
7 | PWMC_CPRE_MCK/128 AT91C_PWMC_CPRE_MCK/128 |
8 | PWMC_CPRE_MCK/256 AT91C_PWMC_CPRE_MCK/256 |
9 | PWMC_CPRE_MCK/512 AT91C_PWMC_CPRE_MCK/512 |
10 | PWMC_CPRE_MCK/1024 AT91C_PWMC_CPRE_MCK/1024 |
11 | PWMC_CPRE_MCKA AT91C_PWMC_CPRE_MCKA |
12 | PWMC_CPRE_MCKB AT91C_PWMC_CPRE_MCKB |
8 | PWMC_CALG AT91C_PWMC_CALG | Channel Alignment 0: The period is left aligned. 1: The period is center aligned.
9 | PWMC_CPOL AT91C_PWMC_CPOL | Channel Polarity 0: The period starts by a low level. 1: The period starts by a high level.
10 | PWMC_CPD AT91C_PWMC_CPD | Channel Update Period 0: Writting to the PWMC_CUPDx will notify the duty cycle at the next period start event. 1: Writting to the PWMC_CUPDx will notify the period at the next period start event.

#### PWMC_CH: AT91_REG PWMC_CDTYR Channel Duty Cycle Register

- PWMC_CH3 AT91C_CH3_CDTYR 0xFFFCC264
- PWMC_CH2 AT91C_CH2_CDTYR 0xFFFCC244
- PWMC_CH1 AT91C_CH1_CDTYR 0xFFFCC224
- PWMC_CH0 AT91C_CH0_CDTYR 0xFFFCC204

Offset | Name | Description
31..0 | PWMC_CDTY AT91C_PWMC_CDTY | Channel Duty Cycle Defines the waveform duty cycle. THis value must be defined between 0 and CPRD(PWMC_CPRx).

#### PWMC_CH: AT91_REG PWMC_CPRDR Channel Period Register

- PWMC_CH3 AT91C_CH3_CPRDR 0xFFFCC268
- PWMC_CH2 AT91C_CH2_CPRDR 0xFFFCC248
- PWMC_CH1 AT91C_CH1_CPRDR 0xFFFCC228
- PWMC_CH0 AT91C_CH0_CPRDR 0xFFFCC208

Offset | Name | Description
31..0 | PWMC_CPRD AT91C_PWMC_CPRD | Channel Period If the waveform is left aligned, its period is CPRD*TMCK. If the waveform is center aligned, its period is 2*CPRD*TMCK.

#### PWMC_CH: AT91_REG PWMC_CCNTR Channel Counter Register

- PWMC_CH3 AT91C_CH3_CCNTR 0xFFFCC26C
- PWMC_CH2 AT91C_CH2_CCNTR 0xFFFCC24C
- PWMC_CH1 AT91C_CH1_CCNTR 0xFFFCC22C
- PWMC_CH0 AT91C_CH0_CCNTR 0xFFFCC20C

Offset | Name | Description
31..0 | PWMC_CCNT AT91C_PWMC_CCNT | Channel Counter Internal Counter Value.

#### PWMC_CH: AT91_REG PWMC_CUPDR Channel Update Register

- PWMC_CH3 AT91C_CH3_CUPDR 0xFFFCC270
- PWMC_CH2 AT91C_CH2_CUPDR 0xFFFCC250
- PWMC_CH1 AT91C_CH1_CUPDR 0xFFFCC230
- PWMC_CH0 AT91C_CH0_CUPDR 0xFFFCC210

Offset | Name | Description
31..0 | PWMC_CUPD AT91C_PWMC_CUPD | Channel Update This register is a double buffer for the period or the duty cycle (CUP in PWMC_CMRx). It prevents from unexpected waveform when modifying waveform period or duty cycle.

#### PWMC_CH: AT91_REG Reserved Reserved

- PWMC_CH3 AT91C_CH3_Reserved 0xFFFCC274
- PWMC_CH2 AT91C_CH2_Reserved 0xFFFCC254
- PWMC_CH1 AT91C_CH1_Reserved 0xFFFCC234
- PWMC_CH0 AT91C_CH0_Reserved 0xFFFCC214