# Peripheral Data Controller Peripheral

PDC_DBGU (AT91S_PDC) 0xFFFFF300 (AT91C_BASE_PDC_DBGU)
PDC_SPI (AT91S_PDC) 0xFFFE0100 (AT91C_BASE_PDC_SPI)
PDC_ADC (AT91S_PDC) 0xFFFD8100 (AT91C_BASE_PDC_ADC)
PDC_SSC (AT91S_PDC) 0xFFFD4100 (AT91C_BASE_PDC_SSC)
PDC_US1 (AT91S_PDC) 0xFFFC4100 (AT91C_BASE_PDC_US1)
PDC_US0 (AT91S_PDC) 0xFFFC0100 (AT91C_BASE_PDC_US0)

## PDC Software API (AT91S_PDC)

Offset | Field | Description
0x0 | PDC_RPR | Receive Pointer Register
0x4 | PDC_RCR | Receive Counter Register
0x8 | PDC_TPR | Transmit Pointer Register
0xC | PDC_TCR | Transmit Counter Register
0x10 | PDC_RNPR | Receive Next Pointer Register
0x14 | PDC_RNCR | Receive Next Counter Register
0x18 | PDC_TNPR | Transmit Next Pointer Register
0x1C | PDC_TNCR | Transmit Next Counter Register
0x20 | PDC_PTCR | PDC Transfer Control Register
0x24 | PDC_PTSR | PDC Transfer Status Register

Function | Description
AT91F_PDC_SetRx | Set the receive transfer descriptor
AT91F_PDC_EnableRx | Enable receive
AT91F_PDC_ReceiveFrame | Close PDC: disable TX and RX reset transfer descriptors
AT91F_PDC_SetTx | Set the transmit transfer descriptor
AT91F_PDC_DisableRx | Disable receive
AT91F_PDC_EnableTx | Enable transmit
AT91F_PDC_IsNextRxEmpty | Test if the next transfer descriptor has been moved to the current td
AT91F_PDC_DisableTx | Disable transmit
AT91F_PDC_Close | Close PDC: disable TX and RX reset transfer descriptors
AT91F_PDC_IsTxEmpty | Test if the current transfer descriptor has been sent
AT91F_PDC_SetNextRx | Set the next receive transfer descriptor
AT91F_PDC_SetNextTx | Set the next transmit transfer descriptor
AT91F_PDC_IsNextTxEmpty | Test if the next transfer descriptor has been moved to the current td
AT91F_PDC_Open | Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
AT91F_PDC_SendFrame | Close PDC: disable TX and RX reset transfer descriptors
AT91F_PDC_IsRxEmpty | Test if the current transfer descriptor has been filled

## PDC Register Description

#### PDC: AT91_REG PDC_RPR Receive Pointer Register

- PDC_DBGU AT91C_DBGU_RPR 0xFFFFF300
- PDC_SPI AT91C_SPI_RPR 0xFFFE0100
- PDC_ADC AT91C_ADC_RPR 0xFFFD8100
- PDC_SSC AT91C_SSC_RPR 0xFFFD4100
- PDC_US1 AT91C_US1_RPR 0xFFFC4100
- PDC_US0 AT91C_US0_RPR 0xFFFC0100

This register must be loaded with the address of the receive buffer

#### PDC: AT91_REG PDC_RCR Receive Counter Register

- PDC_DBGU AT91C_DBGU_RCR 0xFFFFF304
- PDC_SPI AT91C_SPI_RCR 0xFFFE0104
- PDC_ADC AT91C_ADC_RCR 0xFFFD8104
- PDC_SSC AT91C_SSC_RCR 0xFFFD4104
- PDC_US1 AT91C_US1_RCR 0xFFFC4104
- PDC_US0 AT91C_US0_RCR 0xFFFC0104

This register must be loaded with the size of the receive buffer.
0 = Stop peripheral data transfer to the receiver
1 - 65535 = Start peripheral data transfer if corresponding periph_px_rdy is active

#### PDC: AT91_REG PDC_TPR Transmit Pointer Register

- PDC_DBGU AT91C_DBGU_TPR 0xFFFFF308
- PDC_SPI AT91C_SPI_TPR 0xFFFE0108
- PDC_ADC AT91C_ADC_TPR 0xFFFD8108
- PDC_SSC AT91C_SSC_TPR 0xFFFD4108
- PDC_US1 AT91C_US1_TPR 0xFFFC4108
- PDC_US0 AT91C_US0_TPR 0xFFFC0108

This register must be loaded with the address of the transmit buffer

#### PDC: AT91_REG PDC_TCR Transmit Counter Register

- PDC_DBGU AT91C_DBGU_TCR 0xFFFFF30C
- PDC_SPI AT91C_SPI_TCR 0xFFFE010C
- PDC_ADC AT91C_ADC_TCR 0xFFFD810C
- PDC_SSC AT91C_SSC_TCR 0xFFFD410C
- PDC_US1 AT91C_US1_TCR 0xFFFC410C
- PDC_US0 AT91C_US0_TCR 0xFFFC010C

TXCTR must be loaded with the size of the transmit buffer.
0 = Stop peripheral data transfer to the transmitter
1- 65535 = Start peripheral data transfer if corresponding periph_tx_rdy is active

#### PDC: AT91_REG PDC_RNPR Receive Next Pointer Register

- PDC_DBGU AT91C_DBGU_RNPR 0xFFFFF310
- PDC_SPI AT91C_SPI_RNPR 0xFFFE0110
- PDC_ADC AT91C_ADC_RNPR 0xFFFD8110
- PDC_SSC AT91C_SSC_RNPR 0xFFFD4110
- PDC_US1 AT91C_US1_RNPR 0xFFFC4110
- PDC_US0 AT91C_US0_RNPR 0xFFFC0110

contains the address of the next buffer to fill with received data when the current one is completed.

#### PDC: AT91_REG PDC_RNCR Receive Next Counter Register

- PDC_DBGU AT91C_DBGU_RNCR 0xFFFFF314
- PDC_SPI AT91C_SPI_RNCR 0xFFFE0114
- PDC_ADC AT91C_ADC_RNCR 0xFFFD8114
- PDC_SSC AT91C_SSC_RNCR 0xFFFD4114
- PDC_US1 AT91C_US1_RNCR 0xFFFC4114
- PDC_US0 AT91C_US0_RNCR 0xFFFC0114

This register contains the next buffer maximum size.

#### PDC: AT91_REG PDC_TNPR Transmit Next Pointer Register

- PDC_DBGU AT91C_DBGU_TNPR 0xFFFFF318
- PDC_SPI AT91C_SPI_TNPR 0xFFFE0118
- PDC_ADC AT91C_ADC_TNPR 0xFFFD8118
- PDC_SSC AT91C_SSC_TNPR 0xFFFD4118
- PDC_US1 AT91C_US1_TNPR 0xFFFC4118
- PDC_US0 AT91C_US0_TNPR 0xFFFC0118

This register contains the address of the next buffer from where to read data when the current one is complete.

#### PDC: AT91_REG PDC_TNCR Transmit Next Counter Register

- PDC_DBGU AT91C_DBGU_TNCR 0xFFFFF31C
- PDC_SPI AT91C_SPI_TNCR 0xFFFE011C
- PDC_ADC AT91C_ADC_TNCR 0xFFFD811C
- PDC_SSC AT91C_SSC_TNCR 0xFFFD411C
- PDC_US1 AT91C_US1_TNCR 0xFFFC411C
- PDC_US0 AT91C_US0_TNCR 0xFFFC011C

This register contains the next transmit buffer size.

#### PDC: AT91_REG PDC_PTCR PDC Transfer Control Register

- PDC_DBGU AT91C_DBGU_PTCR 0xFFFFF320
- PDC_SPI AT91C_SPI_PTCR 0xFFFE0120
- PDC_ADC AT91C_ADC_PTCR 0xFFFD8120
- PDC_SSC AT91C_SSC_PTCR 0xFFFD4120
- PDC_US1 AT91C_US1_PTCR 0xFFFC4120
- PDC_US0 AT91C_US0_PTCR 0xFFFC0120

Offset | Name | Description
0 | PDC_RXTEN AT91C_PDC_RXTEN | Receiver Transfer Enable PDC_PTCR 0 = No effect. 1 = Enables the receiver PDC2 transfer requests if RXTDIS is not set. PDC_PTSR 0 = Receiver PDC2 transfer requests are disabled. 1 = Receiver PDC2 transfer requests are enabled.
1 | PDC_RXTDIS AT91C_PDC_RXTDIS | Receiver Transfer Disable 0 = No effect. 1 = Disables the receiver PDC2 transfer requests.
8 | PDC_TXTEN AT91C_PDC_TXTEN | Transmitter Transfer Enable PDC_PTCR 0 = No effect. 1 = Enables the transmitter PDC2 transfer requests. PDC_PTSR 0 = Transmitter PDC2 transfer requests are disabled. 1 = Transmitter PDC2 transfer requests are enabled.
9 | PDC_TXTDIS AT91C_PDC_TXTDIS | Transmitter Transfer Disable 0 = No effect. 1 = Disables the transmitter PDC2 transfer requests.

#### PDC: AT91_REG PDC_PTSR PDC Transfer Status Register

- PDC_DBGU AT91C_DBGU_PTSR 0xFFFFF324
- PDC_SPI AT91C_SPI_PTSR 0xFFFE0124
- PDC_ADC AT91C_ADC_PTSR 0xFFFD8124
- PDC_SSC AT91C_SSC_PTSR 0xFFFD4124
- PDC_US1 AT91C_US1_PTSR 0xFFFC4124
- PDC_US0 AT91C_US0_PTSR 0xFFFC0124

Offset | Name | Description
0 | PDC_RXTEN AT91C_PDC_RXTEN | Receiver Transfer Enable PDC_PTCR 0 = No effect. 1 = Enables the receiver PDC2 transfer requests if RXTDIS is not set. PDC_PTSR 0 = Receiver PDC2 transfer requests are disabled. 1 = Receiver PDC2 transfer requests are enabled.
8 | PDC_TXTEN AT91C_PDC_TXTEN | Transmitter Transfer Enable PDC_PTCR 0 = No effect. 1 = Enables the transmitter PDC2 transfer requests. PDC_PTSR 0 = Transmitter PDC2 transfer requests are disabled. 1 = Transmitter PDC2 transfer requests are enabled.