# Advanced Interrupt Controller Peripheral

AIC (AT91S_AIC) 0xFFFFF000 (AT91C_BASE_AIC)

Periph ID AIC | Symbol | Description
0 | (AT91C_ID_FIQ) | Advanced Interrupt Controller (FIQ)
30 | (AT91C_ID_IRQ0) | Advanced Interrupt Controller (IRQ0)
31 | (AT91C_ID_IRQ1) | Advanced Interrupt Controller (IRQ1)

Signal | Symbol | PIO controller | Description
IRQ0 | (AT91C_PA20_IRQ0 ) | PIOA Periph: B Bit: 20 | External Interrupt 0
FIQ | (AT91C_PA19_FIQ ) | PIOA Periph: B Bit: 19 | AIC Fast Interrupt Input
IRQ1 | (AT91C_PA30_IRQ1 ) | PIOA Periph: A Bit: 30 | External Interrupt 1

Function | Description
AT91F_AIC_CfgPIO | Configure PIO controllers to drive AIC signals
AT91F_AIC_CfgPMC | Enable Peripheral clock in PMC for AIC

## AIC Software API (AT91S_AIC)

Offset | Field | Description
0x0 | AIC_SMR[32] (AIC_SMR) | Source Mode Register
0x80 | AIC_SVR[32] (AIC_SVR) | Source Vector Register
0x100 | AIC_IVR | IRQ Vector Register
0x104 | AIC_FVR | FIQ Vector Register
0x108 | AIC_ISR | Interrupt Status Register
0x10C | AIC_IPR | Interrupt Pending Register
0x110 | AIC_IMR | Interrupt Mask Register
0x114 | AIC_CISR | Core Interrupt Status Register
0x120 | AIC_IECR | Interrupt Enable Command Register
0x124 | AIC_IDCR | Interrupt Disable Command Register
0x128 | AIC_ICCR | Interrupt Clear Command Register
0x12C | AIC_ISCR | Interrupt Set Command Register
0x130 | AIC_EOICR | End of Interrupt Command Register
0x134 | AIC_SPU | Spurious Vector Register
0x138 | AIC_DCR | Debug Control Register (Protect)
0x140 | AIC_FFER | Fast Forcing Enable Register
0x144 | AIC_FFDR | Fast Forcing Disable Register
0x148 | AIC_FFSR | Fast Forcing Status Register

Function | Description
AT91F_AIC_SetExceptionVector | Configure vector handler
AT91F_AIC_ClearIt | Clear corresponding IT number
AT91F_AIC_Trig | Trig an IT
AT91F_AIC_Open | Set exception vectors and AIC registers to default values
AT91F_AIC_DisableIt | Disable corresponding IT number
AT91F_AIC_AcknowledgeIt | Acknowledge corresponding IT number
AT91F_AIC_ConfigureIt | Interrupt Handler Initialization
AT91F_AIC_EnableIt | Enable corresponding IT number
AT91F_AIC_IsActive | Test if an IT is active
AT91F_AIC_IsPending | Test if an IT is pending

## AIC Register Description

#### AIC: AT91_REG AIC_SMR Source Mode Register

- AIC AT91C_AIC_SMR 0xFFFFF000

Offset | Name | Description
2..0 | AIC_PRIOR AT91C_AIC_PRIOR | Priority Level Program the priority level for all sources except source 0 (FIQ). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ, in the SMR0. Value | Label | Description
0 | AIC_PRIOR_LOWEST AT91C_AIC_PRIOR_LOWEST | Lowest priority level
7 | AIC_PRIOR_HIGHEST AT91C_AIC_PRIOR_HIGHEST | Highest priority level
6..5 | AIC_SRCTYPE AT91C_AIC_SRCTYPE | Interrupt Source Type Program the input to be positive or negative edge-triggered or positive or negative level sensitive. The active level or edge is not programmable for the internal sources. Value | Label | Description
0 | AIC_SRCTYPE_INT_LEVEL_SENSITIVE AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE | Internal Sources Code Label Level Sensitive
1 | AIC_SRCTYPE_INT_EDGE_TRIGGERED AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED | Internal Sources Code Label Edge triggered
2 | AIC_SRCTYPE_EXT_HIGH_LEVEL AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL | External Sources Code Label High-level Sensitive
3 | AIC_SRCTYPE_EXT_POSITIVE_EDGE AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE | External Sources Code Label Positive Edge triggered

#### AIC: AT91_REG AIC_SVR Source Vector Register

- AIC AT91C_AIC_SVR 0xFFFFF080

The user may store in these registers the addresses of the corresponding handler for each interrupt source.

#### AIC: AT91_REG AIC_IVR IRQ Vector Register

- AIC AT91C_AIC_IVR 0xFFFFF100

The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to
the current interrupt.
The Source Vector Register (1 to 31) is indexed using the current interrupt number when the Interrupt Vector Register is read.
When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU.

#### AIC: AT91_REG AIC_FVR FIQ Vector Register

- AIC AT91C_AIC_FVR 0xFFFFF104

The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0 which corre-sponds to FIQ.

#### AIC: AT91_REG AIC_ISR Interrupt Status Register

- AIC AT91C_AIC_ISR 0xFFFFF108

The Interrupt Status Register returns the current interrupt source number.

#### AIC: AT91_REG AIC_IPR Interrupt Pending Register

- AIC AT91C_AIC_IPR 0xFFFFF10C

0 = Corresponding interrupt is inactive.
1 = Corresponding interrupt is pending.

#### AIC: AT91_REG AIC_IMR Interrupt Mask Register

- AIC AT91C_AIC_IMR 0xFFFFF110

0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.

#### AIC: AT91_REG AIC_CISR Core Interrupt Status Register

- AIC AT91C_AIC_CISR 0xFFFFF114

Offset | Name | Description
0 | AIC_NFIQ AT91C_AIC_NFIQ | NFIQ Status 0 = NFIQ line inactive. 1 = NFIQ line active.
1 | AIC_NIRQ AT91C_AIC_NIRQ | NIRQ Status 0 = NIRQ line inactive. 1 = NIRQ line active.

#### AIC: AT91_REG AIC_IECR Interrupt Enable Command Register

- AIC AT91C_AIC_IECR 0xFFFFF120

0 = No effect.
1 = Enables corresponding interrupt.

#### AIC: AT91_REG AIC_IDCR Interrupt Disable Command Register

- AIC AT91C_AIC_IDCR 0xFFFFF124

0 = No effect.
1 = Disables corresponding interrupt.

#### AIC: AT91_REG AIC_ICCR Interrupt Clear Command Register

- AIC AT91C_AIC_ICCR 0xFFFFF128

0 = No effect.
1 = Clears corresponding interrupt.

#### AIC: AT91_REG AIC_ISCR Interrupt Set Command Register

- AIC AT91C_AIC_ISCR 0xFFFFF12C

0 = No effect.
1 = Sets corresponding interrupt.

#### AIC: AT91_REG AIC_EOICR End of Interrupt Command Register

- AIC AT91C_AIC_EOICR 0xFFFFF130

The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.
Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt
treatment.

#### AIC: AT91_REG AIC_SPU Spurious Vector Register

- AIC AT91C_AIC_SPU 0xFFFFF134

Spurious Interrupt Vector Handler Address
The user may store the address of the spurious interrupt handler in this register.

#### AIC: AT91_REG AIC_DCR Debug Control Register (Protect)

- AIC AT91C_AIC_DCR 0xFFFFF138

Offset | Name | Description
0 | AIC_DCR_PROT AT91C_AIC_DCR_PROT | Protection Mode 0: The protection Mode is disabled 1: The Protection mode is enabled
1 | AIC_DCR_GMSK AT91C_AIC_DCR_GMSK | General Mask 0: The nIRQ qnd nFIQ lines are normally controled by the AIC 1: The nIRQ and nFIQ lines are tied to their inactive mode

#### AIC: AT91_REG AIC_FFER Fast Forcing Enable Register

- AIC AT91C_AIC_FFER 0xFFFFF140

0 = No effect.
1 = Enables fast forcing feature on corresponding interrupt.

#### AIC: AT91_REG AIC_FFDR Fast Forcing Disable Register

- AIC AT91C_AIC_FFDR 0xFFFFF144

0 = No effect.
1 = Disables fast forcing feature on corresponding interrupt.

#### AIC: AT91_REG AIC_FFSR Fast Forcing Status Register

- AIC AT91C_AIC_FFSR 0xFFFFF148

0 = Disabled.
1 = Fast forcing feature enabled on corresponding interrupt.