# Parallel Input Output Controler Peripheral

PIOA (AT91S_PIO) 0xFFFFF400 (AT91C_BASE_PIOA)

Periph ID AIC | Symbol | Description
2 | (AT91C_ID_PIOA) | Parallel IO Controller

Function | Description
AT91F_PIOA_CfgPMC | Enable Peripheral clock in PMC for PIOA

## PIO Software API (AT91S_PIO)

Offset | Field | Description
0x0 | PIO_PER | PIO Enable Register
0x4 | PIO_PDR | PIO Disable Register
0x8 | PIO_PSR | PIO Status Register
0x10 | PIO_OER | Output Enable Register
0x14 | PIO_ODR | Output Disable Registerr
0x18 | PIO_OSR | Output Status Register
0x20 | PIO_IFER | Input Filter Enable Register
0x24 | PIO_IFDR | Input Filter Disable Register
0x28 | PIO_IFSR | Input Filter Status Register
0x30 | PIO_SODR | Set Output Data Register
0x34 | PIO_CODR | Clear Output Data Register
0x38 | PIO_ODSR | Output Data Status Register
0x3C | PIO_PDSR | Pin Data Status Register
0x40 | PIO_IER | Interrupt Enable Register
0x44 | PIO_IDR | Interrupt Disable Register
0x48 | PIO_IMR | Interrupt Mask Register
0x4C | PIO_ISR | Interrupt Status Register
0x50 | PIO_MDER | Multi-driver Enable Register
0x54 | PIO_MDDR | Multi-driver Disable Register
0x58 | PIO_MDSR | Multi-driver Status Register
0x60 | PIO_PPUDR | Pull-up Disable Register
0x64 | PIO_PPUER | Pull-up Enable Register
0x68 | PIO_PPUSR | Pad Pull-up Status Register
0x70 | PIO_ASR | Select A Register
0x74 | PIO_BSR | Select B Register
0x78 | PIO_ABSR | AB Select Status Register
0xA0 | PIO_OWER | Output Write Enable Register
0xA4 | PIO_OWDR | Output Write Disable Register
0xA8 | PIO_OWSR | Output Write Status Register

Function | Description
AT91F_PIO_IsOutputWriteSet | Test if PIO OutputWrite is Set
AT91F_PIO_InterruptDisable | Disable PIO Interrupt
AT91F_PIO_GetOutputDataStatus | Return PIO Output Data Status
AT91F_PIO_GetInput | Return PIO input value
AT91F_PIO_Disable | Disable PIO
AT91F_PIO_IsAB_RegisterSet | Test if PIO AB Register is Set
AT91F_PIO_CfgOutput | Enable PIO in output mode
AT91F_PIO_OutputWriteEnable | Output Write Enable PIO
AT91F_PIO_Enable | Enable PIO
AT91F_PIO_SetOutput | Set to 1 output PIO
AT91F_PIO_GetOutputStatus | Return PIO Output Status
AT91F_PIO_GetOutputWriteStatus | Return PIO Output Write Status
AT91F_PIO_MultiDriverEnable | Multi Driver Enable PIO
AT91F_PIO_B_RegisterSelection | PIO B Register Selection
AT91F_PIO_OutputDisable | Output Enable PIO
AT91F_PIO_Get_AB_RegisterStatus | Return PIO Interrupt Status
AT91F_PIO_IsMultiDriverSet | Test if PIO MultiDriver is Set
AT91F_PIO_InputFilterEnable | Input Filter Enable PIO
AT91F_PIO_GetMultiDriverStatus | Return PIO Multi Driver Status
AT91F_PIO_InterruptEnable | Enable PIO Interrupt
AT91F_PIO_GetCfgPullup | Return PIO Configuration Pullup
AT91F_PIO_CfgInput | Enable PIO in input mode
AT91F_PIO_GetInputFilterStatus | Return PIO Input Filter Status
AT91F_PIO_A_RegisterSelection | PIO A Register Selection
AT91F_PIO_OutputWriteDisable | Output Write Disable PIO
AT91F_PIO_IsInputFilterSet | Test if PIO Input filter is Set
AT91F_PIO_GetInterruptStatus | Return PIO Interrupt Status
AT91F_PIO_CfgDirectDrive | Enable direct drive on PIO
AT91F_PIO_IsSet | Test if PIO is Set
AT91F_PIO_IsInterruptMasked | Test if PIO Interrupt is Masked
AT91F_PIO_MultiDriverDisable | Multi Driver Disable PIO
AT91F_PIO_IsInterruptSet | Test if PIO Interrupt is Set
AT91F_PIO_OutputEnable | Output Enable PIO
AT91F_PIO_InputFilterDisable | Input Filter Disable PIO
AT91F_PIO_IsOutputDataStatusSet | Test if PIO Output Data Status is Set
AT91F_PIO_CfgInputFilter | Enable input filter on input PIO
AT91F_PIO_CfgPeriph | Enable pins to be drived by peripheral
AT91F_PIO_IsCfgPullupStatusSet | Test if PIO Configuration Pullup Status is Set
AT91F_PIO_GetStatus | Return PIO Status
AT91F_PIO_ClearOutput | Set to 0 output PIO
AT91F_PIO_IsInputSet | Test if PIO is input flag is active
AT91F_PIO_IsOuputSet | Test if PIO Output is Set
AT91F_PIO_CfgOpendrain | Configure PIO in open drain
AT91F_PIO_CfgPullup | Enable pullup on PIO
AT91F_PIO_GetInterruptMaskStatus | Return PIO Interrupt Mask Status
AT91F_PIO_ForceOutput | Force output when Direct drive option is enabled

## PIO Register Description

#### PIO: AT91_REG PIO_PER PIO Enable Register

- PIOA AT91C_PIOA_PER 0xFFFFF400

This register is used to enable control of individual pins by the PIO controller rather than by an internally connected periph-eral. When the PIO is enabled, the Data to Peripheral (d_to_periph_a or d_to_periph_b) signal is held at logic zero. The register is programmed as follows:
1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
0 = No effect.

#### PIO: AT91_REG PIO_PDR PIO Disable Register

- PIOA AT91C_PIOA_PDR 0xFFFFF404

This register is used to disable control of individual pins by the PIO controller. When PIO control is disabled, the peripheral function (if any) connected to the I/O channel is enabled to control the corresponding pin. The register is programmed as follows:
1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
0 = No effect.

#### PIO: AT91_REG PIO_PSR PIO Status Register

- PIOA AT91C_PIOA_PSR 0xFFFFF408

This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or dis-abled.The register reads as follows:
1 = PIO is active on the corresponding line (peripheral is inactive).
0 = PIO is inactive on the corresponding line (peripheral is active).

#### PIO: AT91_REG PIO_OER Output Enable Register

- PIOA AT91C_PIOA_OER 0xFFFFF410

This register is used to enable PIO output drivers. If the pin is driven by an internally connected peripheral, PIO_OER has no effect on the pin, but the information is stored. The register is programmed as follows:
1 = Enables the PIO output on the corresponding pin.
0 = No effect.

#### PIO: AT91_REG PIO_ODR Output Disable Registerr

- PIOA AT91C_PIOA_ODR 0xFFFFF414

This register is used to disable PIO output drivers. If the pin is driven by the peripheral, this has no effect on the pin, but the information is stored. The register is programmed as follows:
0 = No effect.
1 = Disables the PIO output on the corresponding pin.

#### PIO: AT91_REG PIO_OSR Output Status Register

- PIOA AT91C_PIOA_OSR 0xFFFFF418

This register shows the PIO pin control (output enable) status which is programmed in PIO_OER and PIO ODR. The defined value is effective only if the pin is controlled by the PIO. The register reads as follows:
0 = The corresponding PIO is input on this line.
1 = The corresponding PIO is output on this line.

#### PIO: AT91_REG PIO_IFER Input Filter Enable Register

- PIOA AT91C_PIOA_IFER 0xFFFFF420

This register is used to enable input glitch filters. It affects the pin whether or not the PIO is enabled. The register is programmed as follows:
0 = No effect.
1 = Enables the glitch filter on the corresponding pin.

#### PIO: AT91_REG PIO_IFDR Input Filter Disable Register

- PIOA AT91C_PIOA_IFDR 0xFFFFF424

This register is used to disable input glitch filters. It affects the pin whether or not the PIO is enabled. The register is pro-grammed as follows:
0 = No effect.
1 = Disables the glitch filter on the corresponding pin.

#### PIO: AT91_REG PIO_IFSR Input Filter Status Register

- PIOA AT91C_PIOA_IFSR 0xFFFFF428

This register indicates which pins have glitch filters selected. It is updated when PIO outputs are enabled or disabled by writing to PIO_IFER or PIO_IFDR.
0 = Filter is not selected on the corresponding input.
1 = Filter is selected on the corresponding input (peripheral and PIO).

#### PIO: AT91_REG PIO_SODR Set Output Data Register

- PIOA AT91C_PIOA_SODR 0xFFFFF430

This register is used to set PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored.
0 = No effect.
1 = PIO output data on the corresponding pin is set.

#### PIO: AT91_REG PIO_CODR Clear Output Data Register

- PIOA AT91C_PIOA_CODR 0xFFFFF434

This register is used to clear PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored.
0 = No effect.
1 = PIO output data on the corresponding pin is cleared.

#### PIO: AT91_REG PIO_ODSR Output Data Status Register

- PIOA AT91C_PIOA_ODSR 0xFFFFF438

This register shows the output data status which is programmed in PIO_SODR or PIO_CODR. The defined value is effec-tive only if the pin is controlled by the PIO Controller and only if the pin is defined as an output.
0 = The output data for the corresponding line is programmed to 0.
1 = The output data for the corresponding line is programmed to 1.

#### PIO: AT91_REG PIO_PDSR Pin Data Status Register

- PIOA AT91C_PIOA_PDSR 0xFFFFF43C

This register shows the logic level of the physical I/O pin. The pin logic levels are always valid, regardless of whether the pins are enabled as PIO, peripheral, input or output. The value of this register will depend on the level of the external pins. The register reads as follows:
1 = The corresponding pin is at logic 1.
0 = The corresponding pin is at logic 0.

#### PIO: AT91_REG PIO_IER Interrupt Enable Register

- PIOA AT91C_PIOA_IER 0xFFFFF440

This register is used to enable PIO interrupts generated by the corresponding pins; logic level changes are detected and stored in the Interrupt Status Register (PIO_ISR). Enabled interrupts will be generated whether the PIO is enabled or not. The register is programmed as follows:
1 = Enables an interrupt when a change of logic level is detected on the corresponding pin.
0 = No effect.

#### PIO: AT91_REG PIO_IDR Interrupt Disable Register

- PIOA AT91C_PIOA_IDR 0xFFFFF444

This register is used to enable PIO interrupts generated by the corresponding pins; logic level changes are detected and stored in the Interrupt Status Register (PIO_ISR). Enabled interrupts will be generated whether the PIO is enabled or not. The register is programmed as follows:
1 = Enables an interrupt when a change of logic level is detected on the corresponding pin.
0 = No effect.

#### PIO: AT91_REG PIO_IMR Interrupt Mask Register

- PIOA AT91C_PIOA_IMR 0xFFFFF448

This register shows which pins have interrupts enabled. It is updated when interrupts are enabled or disabled by writing to PIO_IER or PIO_IDR. The register reads as follows:
1 = Interrupt is enabled from the corresponding pin.
0 = Interrupt is disabled from the corresponding pin.

#### PIO: AT91_REG PIO_ISR Interrupt Status Register

- PIOA AT91C_PIOA_ISR 0xFFFFF44C

This register indicates, for each pin, when a logic level change has been detected (rising or falling edge). This is valid whether the PIO is selected for the pin or not and whether the pin is an input or output. The register is reset to zero following a read, as well as at reset. The register reads as follows:
1 = At least one change has been detected on the corresponding pin since the register was last read or since reset.
0 = No change has been detected on the corresponding pin since the register was last read or since reset.

#### PIO: AT91_REG PIO_MDER Multi-driver Enable Register

- PIOA AT91C_PIOA_MDER 0xFFFFF450

This register shows the logic level of the physical I/O pin. The pin logic levels are always valid, regardless of whether the pins are enabled as PIO, peripheral, input or output. The value of this register will depend on the level of the external pins. The register reads as follows:
1 = The corresponding pin is at logic 1.
0 = The corresponding pin is at logic 0.

#### PIO: AT91_REG PIO_MDDR Multi-driver Disable Register

- PIOA AT91C_PIOA_MDDR 0xFFFFF454

This register shows the logic level of the physical I/O pin. The pin logic levels are always valid, regardless of whether the pins are enabled as PIO, peripheral, input or output. The value of this register will depend on the level of the external pins. The register reads as follows:
1 = The corresponding pin is at logic 1.
0 = The corresponding pin is at logic 0.

#### PIO: AT91_REG PIO_MDSR Multi-driver Status Register

- PIOA AT91C_PIOA_MDSR 0xFFFFF458

This register shows the logic level of the physical I/O pin. The pin logic levels are always valid, regardless of whether the pins are enabled as PIO, peripheral, input or output. The value of this register will depend on the level of the external pins. The register reads as follows:
1 = The corresponding pin is at logic 1.
0 = The corresponding pin is at logic 0.

#### PIO: AT91_REG PIO_PPUDR Pull-up Disable Register

- PIOA AT91C_PIOA_PPUDR 0xFFFFF460

0 = No effect.
1 = Input pad pull-up is disabled.

#### PIO: AT91_REG PIO_PPUER Pull-up Enable Register

- PIOA AT91C_PIOA_PPUER 0xFFFFF464

0 = No effect.
1 = Input pad pull-up is enabled.

#### PIO: AT91_REG PIO_PPUSR Pad Pull-up Status Register

- PIOA AT91C_PIOA_PPUSR 0xFFFFF468

0 = Input pad pull-up is enabled.
1 = Input pad pull-up is disabled with an active low level pull-up control pin.

#### PIO: AT91_REG PIO_ASR Select A Register

- PIOA AT91C_PIOA_ASR 0xFFFFF470

1 = Select peripheral A.
0 = No effect.

#### PIO: AT91_REG PIO_BSR Select B Register

- PIOA AT91C_PIOA_BSR 0xFFFFF474

1 = Select peripheral B.
0 = No effect.

#### PIO: AT91_REG PIO_ABSR AB Select Status Register

- PIOA AT91C_PIOA_ABSR 0xFFFFF478

0 = Peripheral A Selected.
1 = Peripheral B Selected.

#### PIO: AT91_REG PIO_OWER Output Write Enable Register

- PIOA AT91C_PIOA_OWER 0xFFFFF4A0

1 = Enables the possibility to write directly to PIO_ODSR Register.
0 = No effect.

#### PIO: AT91_REG PIO_OWDR Output Write Disable Register

- PIOA AT91C_PIOA_OWDR 0xFFFFF4A4

1 = Disables the possibility to write directly to PIO_ODSR Register.
0 = No effect.

#### PIO: AT91_REG PIO_OWSR Output Write Status Register

- PIOA AT91C_PIOA_OWSR 0xFFFFF4A8

1 = Direct write to PIO_ODSR is enabled.
0 = Direct write to PIO_ODSR is disabled.