# Debug Unit Peripheral

DBGU (AT91S_DBGU) 0xFFFFF200 (AT91C_BASE_DBGU)

Periph ID AIC | Symbol | Description
1 | (AT91C_ID_SYS) | System Peripheral

Signal | Symbol | PIO controller | Description
DTXD | (AT91C_PA10_DTXD ) | PIOA Periph: A Bit: 10 | DBGU Debug Transmit Data
DRXD | (AT91C_PA9_DRXD ) | PIOA Periph: A Bit: 9 | DBGU Debug Receive Data

Function | Description
AT91F_DBGU_CfgPMC | Enable Peripheral clock in PMC for DBGU
AT91F_DBGU_CfgPIO | Configure PIO controllers to drive DBGU signals

## DBGU Software API (AT91S_DBGU)

Offset | Field | Description
0x0 | DBGU_CR | Control Register
0x4 | DBGU_MR | Mode Register
0x8 | DBGU_IER | Interrupt Enable Register
0xC | DBGU_IDR | Interrupt Disable Register
0x10 | DBGU_IMR | Interrupt Mask Register
0x14 | DBGU_CSR | Channel Status Register
0x18 | DBGU_RHR | Receiver Holding Register
0x1C | DBGU_THR | Transmitter Holding Register
0x20 | DBGU_BRGR | Baud Rate Generator Register
0x40 | DBGU_C1R | Chip ID1 Register
0x44 | DBGU_C2R | Chip ID2 Register
0x48 | DBGU_FNTR | Force NTRST Register
0x100 | DBGU_RPR (PDC_RPR) | Receive Pointer Register
0x104 | DBGU_RCR (PDC_RCR) | Receive Counter Register
0x108 | DBGU_TPR (PDC_TPR) | Transmit Pointer Register
0x10C | DBGU_TCR (PDC_TCR) | Transmit Counter Register
0x110 | DBGU_RNPR (PDC_RNPR) | Receive Next Pointer Register
0x114 | DBGU_RNCR (PDC_RNCR) | Receive Next Counter Register
0x118 | DBGU_TNPR (PDC_TNPR) | Transmit Next Pointer Register
0x11C | DBGU_TNCR (PDC_TNCR) | Transmit Next Counter Register
0x120 | DBGU_PTCR (PDC_PTCR) | PDC Transfer Control Register
0x124 | DBGU_PTSR (PDC_PTSR) | PDC Transfer Status Register

Function | Description
AT91F_DBGU_GetInterruptMaskStatus | Return DBGU Interrupt Mask Status
AT91F_DBGU_InterruptDisable | Disable DBGU Interrupt
AT91F_DBGU_IsInterruptMasked | Test if DBGU Interrupt is Masked
AT91F_DBGU_InterruptEnable | Enable DBGU Interrupt

## DBGU Register Description

#### DBGU: AT91_REG DBGU_CR Control Register

- DBGU AT91C_DBGU_CR 0xFFFFF200

Offset | Name | Description
2 | US_RSTRX AT91C_US_RSTRX | Reset Receiver 0 = No effect. 1 = The receiver logic is reset, disabling the receive function (RXDIS is set internally).
3 | US_RSTTX AT91C_US_RSTTX | Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset, disabling the transmit function (TXDIS and STPBRK are set internally).
4 | US_RXEN AT91C_US_RXEN | Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0.
5 | US_RXDIS AT91C_US_RXDIS | Receiver Disable 0 = No effect. 1 = The receiver is disabled.
6 | US_TXEN AT91C_US_TXEN | Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0.
7 | US_TXDIS AT91C_US_TXDIS | Transmitter Disable 0 = No effect. 1 = The transmitter is disabled.

#### DBGU: AT91_REG DBGU_MR Mode Register

- DBGU AT91C_DBGU_MR 0xFFFFF204

Offset | Name | Description
11..9 | US_PAR AT91C_US_PAR | Parity type When the PAR field is set to Even parity, the parity bit is set (“1”) if the data parity is Odd in order to ensure an even parity on the Data and Parity field. Value | Label | Description
0 | US_PAR_EVEN AT91C_US_PAR_EVEN | Even Parity
1 | US_PAR_ODD AT91C_US_PAR_ODD | Odd Parity
2 | US_PAR_SPACE AT91C_US_PAR_SPACE | Parity forced to 0 (Space)
3 | US_PAR_MARK AT91C_US_PAR_MARK | Parity forced to 1 (Mark)
4 | US_PAR_NONE AT91C_US_PAR_NONE | No Parity
6 | US_PAR_MULTI_DROP AT91C_US_PAR_MULTI_DROP | Multi-drop mode
15..14 | US_CHMODE AT91C_US_CHMODE | Channel Mode Value | Label | Description
0 | US_CHMODE_NORMAL AT91C_US_CHMODE_NORMAL | Normal Mode: The USART channel operates as an RX/TX USART.
1 | US_CHMODE_AUTO AT91C_US_CHMODE_AUTO | Automatic Echo: Receiver Data Input is connected to the TXD pin.
2 | US_CHMODE_LOCAL AT91C_US_CHMODE_LOCAL | Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
3 | US_CHMODE_REMOTE AT91C_US_CHMODE_REMOTE | Remote Loopback: RXD pin is internally connected to TXD pin.

#### DBGU: AT91_REG DBGU_IER Interrupt Enable Register

- DBGU AT91C_DBGU_IER 0xFFFFF208

Offset | Name | Description
0 | US_RXRDY AT91C_US_RXRDY | RXRDY Interrupt 0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1 = At least one complete character has been received and the US_RHR has not yet been read.
1 | US_TXRDY AT91C_US_TXRDY | TXRDY Interrupt 0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1 = There is no character in the US_THR. Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.
3 | US_ENDRX AT91C_US_ENDRX | End of Receive Transfer Interrupt 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
4 | US_ENDTX AT91C_US_ENDTX | End of Transmit Interrupt 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.
5 | US_OVRE AT91C_US_OVRE | Overrun Interrupt 0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command. 1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.
6 | US_FRAME AT91C_US_FRAME | Framing Error Interrupt 0 = No stop bit has been detected low since the last Reset Status Bits command. 1 = At least one stop bit has been detected low since the last Reset Status Bits command.
7 | US_PARE AT91C_US_PARE | Parity Error Interrupt 1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command. 0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.
9 | US_TXEMPTY AT91C_US_TXEMPTY | TXEMPTY Interrupt 0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0. Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.
11 | US_TXBUFE AT91C_US_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty
12 | US_RXBUFF AT91C_US_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full.
30 | US_COMM_TX AT91C_US_COMM_TX | COMM_TX Interrupt 0 = COMM_TX is at 0. 1 = COMM_TX is at 1.
31 | US_COMM_RX AT91C_US_COMM_RX | COMM_RX Interrupt 0 = COMM_RX is at 0. 1 = COMM_RX is at 1.

#### DBGU: AT91_REG DBGU_IDR Interrupt Disable Register

- DBGU AT91C_DBGU_IDR 0xFFFFF20C

Offset | Name | Description
0 | US_RXRDY AT91C_US_RXRDY | RXRDY Interrupt 0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1 = At least one complete character has been received and the US_RHR has not yet been read.
1 | US_TXRDY AT91C_US_TXRDY | TXRDY Interrupt 0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1 = There is no character in the US_THR. Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.
3 | US_ENDRX AT91C_US_ENDRX | End of Receive Transfer Interrupt 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
4 | US_ENDTX AT91C_US_ENDTX | End of Transmit Interrupt 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.
5 | US_OVRE AT91C_US_OVRE | Overrun Interrupt 0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command. 1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.
6 | US_FRAME AT91C_US_FRAME | Framing Error Interrupt 0 = No stop bit has been detected low since the last Reset Status Bits command. 1 = At least one stop bit has been detected low since the last Reset Status Bits command.
7 | US_PARE AT91C_US_PARE | Parity Error Interrupt 1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command. 0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.
9 | US_TXEMPTY AT91C_US_TXEMPTY | TXEMPTY Interrupt 0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0. Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.
11 | US_TXBUFE AT91C_US_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty
12 | US_RXBUFF AT91C_US_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full.
30 | US_COMM_TX AT91C_US_COMM_TX | COMM_TX Interrupt 0 = COMM_TX is at 0. 1 = COMM_TX is at 1.
31 | US_COMM_RX AT91C_US_COMM_RX | COMM_RX Interrupt 0 = COMM_RX is at 0. 1 = COMM_RX is at 1.

#### DBGU: AT91_REG DBGU_IMR Interrupt Mask Register

- DBGU AT91C_DBGU_IMR 0xFFFFF210

Offset | Name | Description
0 | US_RXRDY AT91C_US_RXRDY | RXRDY Interrupt 0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1 = At least one complete character has been received and the US_RHR has not yet been read.
1 | US_TXRDY AT91C_US_TXRDY | TXRDY Interrupt 0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1 = There is no character in the US_THR. Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.
3 | US_ENDRX AT91C_US_ENDRX | End of Receive Transfer Interrupt 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
4 | US_ENDTX AT91C_US_ENDTX | End of Transmit Interrupt 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.
5 | US_OVRE AT91C_US_OVRE | Overrun Interrupt 0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command. 1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.
6 | US_FRAME AT91C_US_FRAME | Framing Error Interrupt 0 = No stop bit has been detected low since the last Reset Status Bits command. 1 = At least one stop bit has been detected low since the last Reset Status Bits command.
7 | US_PARE AT91C_US_PARE | Parity Error Interrupt 1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command. 0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.
9 | US_TXEMPTY AT91C_US_TXEMPTY | TXEMPTY Interrupt 0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0. Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.
11 | US_TXBUFE AT91C_US_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty
12 | US_RXBUFF AT91C_US_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full.
30 | US_COMM_TX AT91C_US_COMM_TX | COMM_TX Interrupt 0 = COMM_TX is at 0. 1 = COMM_TX is at 1.
31 | US_COMM_RX AT91C_US_COMM_RX | COMM_RX Interrupt 0 = COMM_RX is at 0. 1 = COMM_RX is at 1.

#### DBGU: AT91_REG DBGU_CSR Channel Status Register

- DBGU AT91C_DBGU_CSR 0xFFFFF214

Offset | Name | Description
0 | US_RXRDY AT91C_US_RXRDY | RXRDY Interrupt 0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1 = At least one complete character has been received and the US_RHR has not yet been read.
1 | US_TXRDY AT91C_US_TXRDY | TXRDY Interrupt 0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1 = There is no character in the US_THR. Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.
3 | US_ENDRX AT91C_US_ENDRX | End of Receive Transfer Interrupt 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.
4 | US_ENDTX AT91C_US_ENDTX | End of Transmit Interrupt 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.
5 | US_OVRE AT91C_US_OVRE | Overrun Interrupt 0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command. 1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.
6 | US_FRAME AT91C_US_FRAME | Framing Error Interrupt 0 = No stop bit has been detected low since the last Reset Status Bits command. 1 = At least one stop bit has been detected low since the last Reset Status Bits command.
7 | US_PARE AT91C_US_PARE | Parity Error Interrupt 1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command. 0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.
9 | US_TXEMPTY AT91C_US_TXEMPTY | TXEMPTY Interrupt 0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0. Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.
11 | US_TXBUFE AT91C_US_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty
12 | US_RXBUFF AT91C_US_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full.
30 | US_COMM_TX AT91C_US_COMM_TX | COMM_TX Interrupt 0 = COMM_TX is at 0. 1 = COMM_TX is at 1.
31 | US_COMM_RX AT91C_US_COMM_RX | COMM_RX Interrupt 0 = COMM_RX is at 0. 1 = COMM_RX is at 1.

#### DBGU: AT91_REG DBGU_RHR Receiver Holding Register

- DBGU AT91C_DBGU_RHR 0xFFFFF218

Last character received if RXRDY is set. When number of data bits is less than 8 bits, the bits are right-aligned. All non-sig-nificant bits read zero.

#### DBGU: AT91_REG DBGU_THR Transmitter Holding Register

- DBGU AT91C_DBGU_THR 0xFFFFF21C

Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than 8 bits, the bits are right-aligned.

#### DBGU: AT91_REG DBGU_BRGR Baud Rate Generator Register

- DBGU AT91C_DBGU_BRGR 0xFFFFF220

Clock Divisor:
0 Disables Clock
1 Clock Divisor Bypass
2 to 65535 Baud Rate = Selected Clock / (CDx16)

#### DBGU: AT91_REG DBGU_C1R Chip ID1 Register

- DBGU AT91C_DBGU_C1R 0xFFFFF240

Hard-coded value. Must be specified before debug unit synthesis.

#### DBGU: AT91_REG DBGU_C2R Chip ID2 Register

- DBGU AT91C_DBGU_C2R 0xFFFFF244

Hard-coded value. Must be specified before debug unit synthesis.

#### DBGU: AT91_REG DBGU_FNTR Force NTRST Register

- DBGU AT91C_DBGU_FNTR 0xFFFFF248

Offset | Name | Description
0 | US_FORCE_NTRST AT91C_US_FORCE_NTRST | Force NTRST in JTAG 0 = NTRST is not forced. 1 = NTRST is forced.

#### DBGU: AT91S_PDC DBGU_PDC PDC interface

- DBGU AT91C_DBGU_DBGU 0xFFFFF300