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Introduction
The OKI ML67Q500x is high-performance CMOS 32-bit micro-controller combines the 32-bit ARM7TDMITM core, a RISC CPU developed by Advanced RISC Machines Limited (ARM), with a DMA controller, serial ports, PWM generator, analog-to-digital converter, 16-bit timers, and other peripheral functions on a single LSI. In addition to 32-bit data processing, this LSI includes internal RAM and onboard peripherals that make it ideal for such embedded control applications as PC peripherals and communication terminals. Finally, there is a built-in external memory controller for directly connecting ROM, SRAM, SDRAM, other memory types, and peripheral devices.
The OKI-E67Q500x Development board is designed to evaluate ML67Q500x processor. It has the following features: - single power supply: 6V AC or DC required - status led and power indicator led - Compact Flash (CF) connector - SD/MMC connector - RESET supervisor IC and button - extension port for ETHERNET with CS8900A - extension port for CPU header board - LCD16x2 with BACKLIGHT - RS232 driver and connector - four buttons - extension ports - power jack - PCB: FR-4, 1.5 mm (0,062"), green soldermask, white silkscreen component print - Dimensions: 160x115 mm (6.3x4.5")
The purpose of this guide is to describe AT91SAM7-P64 Development board.
Board | OKI-E67Q500x
Hardware details | Describes the hardware peripherials in detail
Programming | describes how to write programs for the OKI-E67Q500x Board.
Revision | 01.01.2005 Creating
Copyright (c) OLIMEX Ltd. All rights reserved


Picture

This is picture of OKI-E67Q500X Development board.

Board OKI-E67Q500X

Copyright (c) OLIMEX Ltd. All rights reserved


OKI-E67Q500X


OKI-E67Q500X Board

Notice: EXT - CPU extension port

Copyright (c) OLIMEX Ltd. All rights reserved


AT91SAM7-P64 Hardware description

Peripherials

Unit | Description
COM Port1 | RS232 DB9 Female connector linked to OKI ML67Q500x SIO interface.
CPU extension port | Extension port for CPU header board.
LAN extension port | Extension port for LAN header board (with CS8900A)
CF connector | Connector for external Compact Flash cards.
SD/MMC connector | Connector for external SD/MMC cards.
LCD Display | 2X16 LCD Display
Extension ports | 2x7 pins, 0,1" extension ports EXT1
Optocouple | Optocouple1 connected to connected to CPU extension port - EXT3_25 ( PIOE[6] / EXTINT_N[1] ) Optocouple2 connected to connected to CPU extension port - EXT3_27 (PIOE[8] / EXTINT_N[3] )
Buttons | Button1 connected to CPU extension port - EXT3_3 ( PIOA[2] / CTS ) Button2 connected to CPU extension port - EXT3_4 ( PIOA[3] / DSR ) Button3 connected to CPU extension port - EXT3_5 ( PIOA[4] / DCD ) Button4 connected to CPU extension port - EXT3_8 ( PIOA[7] / RI )
Relay | Relay1 connected to CPU extension port - EXT3_6 ( PIOA[5] / DTR ) Relay2 connected to CPU extension port - EXT3_7 ( PIOA[6] / RTS )
Led | Red status led (Led2) connected to CPU extension port - EXT2_21 ( PIOD[0] / XWAIT ) via Jumper 1 Red power led indicator (Led1)

Notice: EXT3_3 means - Extension port 3, 3th pin.

Technical characteristics

Parameter | Description
Voltage Supply | min 6.0V DC, max 9.0V DC min 4.5V AC, max 6.0V AC
CPU | ML67Q500x
Board dimensions | 160x115 mm (6.3x4.5")
PCB | FR-4, 1.5 mm (0,062"), green soldermask, white silkscreen component print
Operating Temperature | form 0ºC to 70ºC

Extension port 1

Pin / Name | Connected to: | Functionality
1 - AIN2 | AEXT_7 | AINT2
2 - - | not connected | -
3 - AIN3 | AEXT_9 | AIN3
4 - ST_LED_H | EXT2_20 | PIOC[7] / XWR
5 - VREFP | AEXT_2 | VREFP
6 - PIOB4 | EXT3_13 | PIOB[4] / TCOUT[0]
7 - VREFN | AEXT_4 | VREFN
8 - PIOB5 | EXT3_14 | PIOB[5] / TCOUT[1]
9 - ST_LED_M | EXT2_21 | PIOD[0] / XWAIT
10 - PIOC0 | EXT3_17 | PIOC[0] / PWMOUT[0]
11 - 5V_USB_OUT | +5V | -
12 - PIOC1 | EXT3_18 | PIOC[1] / PWMOUT[1]
13 - VCC | VCC | -
14 - PIOE3 | EXT3_22 | PIOE[3] / SDA
15 - +5V | +5V | -
16 - PIOE4 | EXT3_23 | PIOE[4] / SCL
17 - VIN | EXT2_31 EXT2_32 | VIN1 VIN2
18 - PIOE5 | EXT3_24 | PIOE[5] / EXTINT_N[0]
19 - GND | GROUND | -
20 - GND | GROUND | -

RS232 Connector (RS232)

Pin / Name | Connected to: | Functionality
1 - CD | not connected | -
2 - RXD | CPU extension port | PIOB[7] / RXD
3 - TXD | CPU extension port | PIOB[6] / TXD
4 - DTR | not connected | -
5 - GND | GROUND | -
6 - DSR | not connected | -
7 - RTS | not connected | -
8 - CTS | not connected | -
9 - RI | not connected | -

CF Connector

Pin / Name | Connected to: | Functionality
1 - GND1 | GROUND | -
2 - D03 | EXT2_4 | D3
3 - D04 | EXT2_5 | D4
4 - D05 | EXT2_6 | D5
5 - D06 | EXT2_7 | D6
6 - D07 | EXT2_8 | D7
7 - CS0 | EXT1_32 | IOCS_N1
8 - A10 | GROUND | -
9 - ATA_SEL | GROUND | -
10 - A09 | GROUND | -
11 - A08 | GROUND | -
12 - A07 | GROUND | -
13 - VCC1 | +3.3V | -
14 - A06 | GROUND | -
15 - A05 | GROUND | -
16 - A04 | GROUND | -
17 - A03 | GROUND | -
18 - A02 | EXT1_4 | A3
19 - A01 | EXT1_3 | A2
20 - A00 | EXT1_2 | A0
21 - D00 | EXT2_1 | D0
22 - D01 | EXT2_2 | D1
23 - D02 | EXT2_3 | D2
24 - IOCS16 | not connected | -
25 - CD2 | EXT3_10 | PIOB[1] / DREQCLR[0]
26 - CD1 | EXT3_10 | PIOB[1] / DREQCLR[0]
27 - D11 | EXT2_12 | D11
28 - D12 | EXT2_13 | D12
29 - D13 | EXT2_14 | D13
30 - D14 | EXT2_15 | D14
31 - D15 | EXT2_16 | D15
32 - CS1 | EXT1_33 | IOCS_N2
33 - VS1 | not connected |
34 - IORD | EXT1_25 | XOE_N
35 - IOWR | EXT1_26 | XWE_N
36 - WE | +3.3V | -
37 - INTRQ | EXT3_26 | PIOE[7] / EXTINT_N[2]
38 - VCC2 | +3.3V | -
39 - CSEL | GROUND | -
40 - VS2 | not connected | -
41 - RESET | EXT3_14 | PIOB[5] / DTR
42 - IORDY | not connected | -
43 - INPACK | not connected | -
44 - REG | +3.3V | -
45 - DASP | not connected | -
46 - PDIAG | not connected | -
47 - D08 | EXT2_9 | D8
48 - D09 | EXT2_10 | D9
49 - D10 | EXT2_11 | D10
50 - GND2 | GROUND | -

SD/MMC Connector

Pin / Name | Connected to: | Functionality
1 - CD/DAT3/CS | EXT3_9 | PIOB[0] / DREQ[0]
2 - CMD/DI | EXT3_21 | PIOE[2] / SDO
3 - VSS1 | GROUND | -
4 - VDD | +3.3V | -
5 - CLK/SCLK | EXT3_19 | PIOE[0] / SCLK
6 - VSS2 | GROUND | -
7 - DAT0/DO | EXT3_20 | PIOE[1] / SDI
8 - DAT1/RES | not connected | -
9 - DAT2/RES | not connected | -
10 - WP1 | EXT3_11 | PIOB[2] / DREQ[1]
11 - WP2 | +3.3V | -
12 - CP1 | +3.3V | -
13 - CP2 | EXT3_12 | PIOB[3] / DREQCLR[1]

WP - write protect
CP - card present

Jumpers

Jumpers | Position | Description
Jumper 1 (LED) |  | RED led is not connected
 |  | RED led connected to EXT2_21 ( PIOD[0] / XWAIT )


Links

1. OKI Semiconductors web site

OKI product datasheets, application notes, etc info:
http://www.okisemi.com/

2. OKI microcontrollers discussion forum

http://groups.yahoo.com/group/arm-olimex/ - forum for discussions on Olimex ARM boards

3. IAR Systems EW-ARM C compiler and debugger

http://www.iar.com/Products/?name=EWARM

4. Rowley associates CrossWorks for ARM C compiler and debugger

http://www.rowley.co.uk


Programming: RS232

RS232 Connector

Pin / Name | Description
1 - CD | Carrier Detected.
2 - RXD | Received Data.
3 - TXD | Transmited Data.
4 - DTR | Data Terminal Ready.
5 - GND | Signal Ground.
6 - DSR | Data Set Ready.
7 - RTS | Request to Send.
8 - CTS | Clear to Send..
9 - RI | Ring Indicator.

Register description

Register | Address | Function
UARTRBR | 0xB7B00000 | Receiver Buffer Register.
UARTTHR | 0xB7B00000 | Transmitter Holding Register.
UARTIER | 0xB7B00004 | Interrupt Enable Register.
UARTIIR | 0xB7B00008 | Interrupt Identification Register.
UARTFCR | 0xB7B00008 | FIFO Control Register.
UARTLCR | 0xB7B0000C | Line Control Register.
UARTMCR | 0xB7B00010 | Modem Control Register.
UARTLSR | 0xB7B00014 | Line Status Register.
UARTMSR | 0xB7B00018 | Modem Status Register.
UARTSCR | 0xB7B0001C | Scratch Register.
UARTDLL | 0xB7B00000 | Divisor Latch (LSB).
UARTDLM | 0xB7B00004 | Divisor Latch (MSB).

1.Initialization

1.1. Set Control Register
UARTLCR | Function | Description
0:1 | LCR[1:0] | These bits specify the character length (5 to 8 bits). 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits
2 | LCR[2] | This bit specifies the number of stop bits for transmitting characters. 0: 1 stop bits 1: 2 stop bits (1.5 for character length = 5)
3 | LCR[3] | This bit controls the use of parity. 0: No parity 1: Parity used
4 | LCR[4] | This bit specifies even or odd parity. This setting is only valid, however, when parity is enabled (LCR[3] = “1”). 0: Odd parity. 1: Even parity.
5 | LCR[5] | Stick parity. A “1” in this bit sets all parity bits to a fixed value, the inverse of the bit in LCR[4]. This setting is only valid, however, when parity is enabled (LCR[3] = “1”). The receiver can therefore check the parity using a known state. LCR[5] LCR[4] LCR[3] 0 0 1 Odd parity 0 1 1 Even parity 1 0 1 Fixed parity (“1”) 1 1 1 Fixed parity (“0”)
6 | LCR[6] | Break control. Setting this bit to “1” sends a break signal by driving the serial output (SOUT) at Low level, or spacing state. Setting this bit to “0” disables the break. This break control function affects only SOUT, masking SOUT output. The transmit operation continues internally. The CPU can use this break control function to send a warning to the computer communications system terminal. 0: Normal operation. 1: Transmit break signal.
7 | LCR[6] | Divisor latch access bit (DLAB). This bit switches access between UARTDLL and UARTDLM and UARTRBR, UARTTHR, and UARTIER. 0: Normal operation (accessing UARTRBR, UARTTHR, UARTIIR) 1: Divisor latch (UARTDLL and UARTDLM) access..

1.2 Set Baud Rate

Divisor Latch (LSB) (UARTDLL) This register contains the lower half of the 16-bit divisor latch for the baud rate generator. For further details, see the section on baud rate clock generation. The CPU has read/write access to this register when LCR[7] = 1. The register contents after a reset are indeterminate.

Divisor Latch (MSB) (UARTDLM) This register contains the upper half of the 16-bit divisor latch for the baud rate generator. For further details, see the section on baud rate clock generation. The CPU has read/write access to this register when LCR[7] = 1. The register contents after a reset are indeterminate.

Baud rate frequency = CCLK / (devisor x 16)

1.3. Set Functionality to pins

Set second functionality to pins.

2. RS232 Communication

2.1. Write to RS232

Use follow algorithm to send data:
- fill US_THR register with data to write
- wait shift all data

2.2. Read from RS232

Use follow algorithm to receive data:
- wait read all data
- get data from U0RBR

3. Example

 //Baud rate
    frequency = CCLK/(devisor x 16)
//devisor = CCLK/(Baud rate frequency x 16)
//CCLK = 14 745 600
//Baud rate frequency = 9 600
//calculate -> devisor = 0x60
//
//CCLK = 20 000 000
//Baud rate frequency = 9 600
//calculate -> devisor = 0x83

unsigned short divisor = 0x83;

UARTLCR_bit.LCR10 = 0x3;
    //8 bit
UARTLCR_bit.LCR2 = 0x0;
    //1 stop bit
UARTLCR_bit.LCR3 = 0x0;
    //no parity
UARTLCR_bit.LCR7 = 0x1;
    //enable DLAB

UARTDLL = divisor & 0xFF;        //set
    low byte from the 16-bit divisor.
UARTDLM = (divisor >> 8) & 0xFF; //set igh byte from the 16-bit divisor.
UARTLCR_bit.LCR7 = 0x0;
    //disable DLAB

GPCTL_bit.GPCTL0 = 1;
    //set second function of port.

Read Data:
   while (UARTLSR_bit.LSR0 != 1);
   return UARTRBR;

Write Data:
while (UARTLSR_bit.LSR5
    != 1);
UARTTHR = a;