mcu.h

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00001 /*H**************************************************************************
00002 * NAME:         mcu.h
00003 *----------------------------------------------------------------------------
00004 * Copyright (c) 2006 Atmel.
00005 *----------------------------------------------------------------------------
00006 * RELEASE:      at90usb162-cdc-1_0_1
00007 * REVISION:     1.2
00008 *----------------------------------------------------------------------------
00009 * PURPOSE:
00010 * SFR Description file for at90usb16.
00011 *****************************************************************************/
00012 #ifndef MCU_H
00013 #define MCU_H
00014 
00015 /*==========================*/
00016 /* Predefined SFR Addresses */
00017 /*==========================*/
00018 
00019 /******************************************************************************/
00020 #if defined(__ICCAVR__) || defined(__IAR_SYSTEMS_ASM__)
00021 /******************************************************************************/
00022 
00023 SFR_B(PINB,   0x03)   /* Input Pins, Port B                      */
00024 SFR_B(DDRB,   0x04)   /* Data Direction Register, Port B         */
00025 SFR_B(PORTB,  0x05)   /* Data Register, Port B                   */
00026 
00027 SFR_B(PINC,   0x06)   /* Input Pins, Port C                      */
00028 SFR_B(DDRC,   0x07)   /* Data Direction Register, Port C         */
00029 SFR_B(PORTC,  0x08)   /* Data Register, Port C                   */
00030 
00031 SFR_B(PIND,   0x09)   /* Input Pins, Port D                      */
00032 SFR_B(DDRD,   0x0A)   /* Data Direction Register, Port D         */
00033 SFR_B(PORTD,  0x0B)   /* Data Register, Port D                   */
00034 
00035 SFR_B(TIFR0,  0x15)   /* Timer/Counter Interrupt Flag register 0 */
00036 SFR_B(TIFR1,  0x16)   /* Timer/Counter Interrupt Flag register 1 */
00037 
00038 SFR_B(PCIFR,  0x1B)   /* Pin Change Interrupt Flag Register      */
00039 
00040 SFR_B(EIFR,   0x1C)   /* External Interrupt Flag Register        */
00041 SFR_B(EIMSK,  0x1D)   /* External Interrupt Mask Register        */
00042 
00043 SFR_B(GPIOR0, 0x1E)   /* General Purpose Register 0              */
00044 
00045 SFR_B(EECR,   0x1F)   /* EEPROM Control Register                 */
00046 SFR_B(EEDR,   0x20)   /* EEPROM Data Register                    */
00047 SFR_W(EEAR,   0x21)   /* EEPROM Address Register                 */
00048 
00049 SFR_B(GTCCR,  0x23)   /* General Purpose Register                */
00050 
00051 SFR_B(TCCR0A, 0x24)   /* Timer/Counter 0 Control Register        */
00052 SFR_B(TCCR0B, 0x25)   /* Timer/Counter 0 Control Register        */
00053 SFR_B(TCNT0,  0x26)   /* Timer/Counter 0                         */
00054 SFR_B(OCR0A,  0x27)   /* Timer/Counter 0 Output Compare Register */
00055 SFR_B(OCR0B,  0x28)   /* Timer/Counter 0 Output Compare Register */
00056 
00057 SFR_B(PLLCSR, 0x29)   /* PLL Control and Status Register         */
00058 
00059 SFR_B(GPIOR1, 0x2A)   /* General Purpose Register 1              */
00060 SFR_B(GPIOR2, 0x2B)   /* General Purpose Register 2              */
00061 
00062 SFR_B(SPCR,   0x2C)   /* SPI Control Register                    */
00063 SFR_B(SPSR,   0x2D)   /* SPI Status Register                     */
00064 SFR_B(SPDR,   0x2E)   /* SPI I/O Data Register                   */
00065 
00066 SFR_B(ACSR,   0x30)   /* Analog Comparator Control and Status Register */
00067 
00068 SFR_B(DWDR,   0x31)   /* DebugWire Register                      */
00069 
00070 SFR_B(SMCR,   0x33)   /* Sleep Mode Control Register             */
00071 SFR_B(MCUSR,  0x34)   /* MCU Status Register                     */
00072 SFR_B(MCUCR,  0x35)   /* MCU Control Register                    */
00073 
00074 SFR_B(SPMCSR, 0x37)   /* Store Program Memory Control and Status Register */
00075 
00076 SFR_W(SP,     0x3D)   /* Stack Pointer                           */
00077 SFR_B(SREG,   0x3F)   /* Status Register                         */
00078 
00079 SFR_B_EXT(WDTCR,   0x60)   /* Watchdog Timer Control Register for compatibility */
00080 SFR_B_EXT(WDTCSR,  0x60)   /* Watchdog Timer Control Register                   */
00081 SFR_B_EXT(CLKPR,   0x61)   /* Clock Prescale Register                           */
00082 
00083 SFR_B_EXT(REGCR,   0x63)   /* Regulator Control Register */
00084 
00085 SFR_B_EXT(OSCCAL,  0x66)   /* Oscillator Calibration Register                   */
00086 
00087 SFR_B_EXT(PCICR,   0x68)   /* Pin Change interrupt enable                       */
00088 
00089 SFR_B_EXT(EICRA,   0x69)   /* External Interrupt Control Register A             */
00090 SFR_B_EXT(EICRB,   0x6A)   /* External Interrupt Control Register B             */
00091 
00092 SFR_B_EXT(PCMSK0,  0x6B)   /* Pin Change interrupt mask                         */
00093 SFR_B_EXT(PCMSK1,  0x6C)   /* Pin Change interrupt mask                         */
00094 
00095 SFR_B_EXT(TIMSK0,  0x6E)   /* Timer/Counter 0 Interrupt Mask Register           */
00096 SFR_B_EXT(TIMSK1,  0x6F)   /* Timer/Counter 1 Interrupt Mask Register           */
00097 
00098 SFR_B_EXT(TCCR1A,  0x80)   /* Timer/Counter 1 Control Register A                */
00099 SFR_B_EXT(TCCR1B,  0x81)   /* Timer/Counter 1 Control Register B                */
00100 SFR_B_EXT(TCCR1C,  0x82)   /* Timer/Counter 1 Control Register C                */
00101 SFR_W_EXT(TCNT1,   0x84)   /* Timer/Counter 1 Register                          */
00102 SFR_W_EXT(ICR1,    0x86)   /* Timer/Counter 1 Input Capture Register            */
00103 SFR_W_EXT(OCR1A,   0x88)   /* Timer/Counter 1 Output Compare Register A         */
00104 SFR_W_EXT(OCR1B,   0x8A)   /* Timer/Counter 1 Output Compare Register B         */
00105 SFR_W_EXT(OCR1C,   0x8C)   /* Timer/Counter 1 Output Compare Register C         */
00106 
00107 SFR_B_EXT(UCSR1A,  0xC8)   /* USART1 Control and Status Register A              */
00108 SFR_B_EXT(UCSR1B,  0xC9)   /* USART1 Control and Status Register B              */
00109 SFR_B_EXT(UCSR1C,  0xCA)   /* USART1 Control and Status Register C              */
00110 SFR_B_EXT(UCSR1D,  0xCB)   /* USART1 Control and Status Register D              */
00111 SFR_W_EXT(UBRR1,   0xCC)   /* USART1 Baud Rate Register Low                     */
00112 SFR_B_EXT(UDR1,    0xCE)   /* USART1 I/O Data Register                          */
00113 
00114 
00115 // USB CONTROLLER
00116 // USB General
00117 // Page 1
00118 SFR_B_EXT(USBCON,    0xD8);
00119 SFR_B_EXT(UDPADDL,   0xDB);
00120 SFR_B_EXT(UDPADDH,   0xDC);
00121 
00122 // USB Device
00123 // Page 1
00124 SFR_B_EXT(UDCON,     0xE0);
00125 SFR_B_EXT(UDINT,     0xE1);
00126 SFR_B_EXT(UDIEN,     0xE2);
00127 SFR_B_EXT(UDADDR,    0xE3);
00128 SFR_B_EXT(UDFNUML,   0xE4);
00129 SFR_B_EXT(UDFNUMH,   0xE5);
00130 SFR_B_EXT(UDMFN,     0xE6);
00131 SFR_B_EXT(UDTST,     0xE7);
00132 
00133 // USB Endpoint
00134 // Page 1
00135 SFR_B_EXT(UENUM,     0xE9);
00136 SFR_B_EXT(UERST,     0xEA);
00137 SFR_B_EXT(UECONX,    0xEB);
00138 SFR_B_EXT(UECFG0X,   0xEC);
00139 SFR_B_EXT(UECFG1X,   0xED);
00140 SFR_B_EXT(UESTA0X,   0xEE);
00141 SFR_B_EXT(UESTA1X,   0xEF);
00142 SFR_B_EXT(UEINTX,    0xE8);
00143 SFR_B_EXT(UEIENX,    0xF0);
00144 SFR_B_EXT(UEDATX,    0xF1);
00145 SFR_B_EXT(UEBCLX,    0xF2);
00146 SFR_B_EXT(UEINT,     0xF4);
00147 
00148 // PS2 and USB
00149 SFR_B_EXT(PS2CON,    0xFA);
00150 SFR_B_EXT(UPOE,      0xFB);
00151 
00152 // Clock Switching
00153 SFR_B_EXT(CKSEL0,    0xD0);
00154 SFR_B_EXT(CKSEL1,    0xD1);
00155 SFR_B_EXT(CKSTA,     0xD2);
00156 
00157 
00158 /*==============================*/
00159 /* Interrupt Vector Definitions */
00160 /*==============================*/
00161 /* NB! vectors are specified as byte addresses */
00162 #define    RESET_vect                  (0x00)
00163 #define    INT0_vect                   (0x04)
00164 #define    INT1_vect                   (0x08)
00165 #define    INT2_vect                   (0x0C)
00166 #define    INT3_vect                   (0x10)
00167 #define    INT4_vect                   (0x14)
00168 #define    INT5_vect                   (0x18)
00169 #define    INT6_vect                   (0x1C)
00170 #define    INT7_vect                   (0x20)
00171 #define    PCINT0_vect                 (0x24)
00172 #define    PCINT1_vect                 (0x28)
00173 #define    USB_GENERAL_vect            (0x2C)
00174 #define    USB_ENDPOINT_vect           (0x30)
00175 #define    WDT_vect                    (0x34)
00176 #define    TIMER1_CAPT_vect            (0x38)
00177 #define    TIMER1_COMPA_vect           (0x3C)
00178 #define    TIMER1_COMPB_vect           (0x40)
00179 #define    TIMER1_COMPC_vect           (0x44)
00180 #define    TIMER1_OVF_vect             (0x48)
00181 #define    TIMER0_COMPA_vect           (0x4C)
00182 #define    TIMER0_COMPB_vect           (0x50)
00183 #define    TIMER0_OVF_vect             (0x54)
00184 #define    SPI_STC_vect                (0x58)
00185 #define    USART1_RXC_vect             (0x5C)
00186 #define    USART1_UDRE_vect            (0x60)
00187 #define    USART1_TXC_vect             (0x64)
00188 #define    ANA_COMP_vect               (0x68)
00189 #define    EE_RDY_vect                 (0x6C)
00190 #define    SPM_RDY_vect                (0x70)
00191 //#define                                (0x74)
00192 
00193 #endif /* _IAR_ */
00194 /******************************************************************************/
00195 #ifdef __CODEVISIONAVR__
00196 /******************************************************************************/
00197 
00198 #define PINB    (*(volatile unsigned char *)0x23) /* Input Pins, Port B                      */
00199 #define DDRB    (*(volatile unsigned char *)0x24) /* Data Direction Register, Port B         */
00200 #define PORTB   (*(volatile unsigned char *)0x25) /* Data Register, Port B                   */
00201 
00202 #define PINC    (*(volatile unsigned char *)0x26) /* Input Pins, Port C                      */
00203 #define DDRC    (*(volatile unsigned char *)0x27) /* Data Direction Register, Port C         */
00204 #define PORTC   (*(volatile unsigned char *)0x28) /* Data Register, Port C                   */
00205 
00206 #define PIND    (*(volatile unsigned char *)0x29) /* Input Pins, Port D                      */
00207 #define DDRD    (*(volatile unsigned char *)0x2A) /* Data Direction Register, Port D         */
00208 #define PORTD   (*(volatile unsigned char *)0x2B) /* Data Register, Port D                   */
00209 
00210 #define TIFR0   (*(volatile unsigned char *)0x35) /* Timer/Counter Interrupt Flag register 0 */
00211 #define TIFR1   (*(volatile unsigned char *)0x36) /* Timer/Counter Interrupt Flag register 1 */
00212 
00213 #define PCIFR   (*(volatile unsigned char *)0x3B) /* Pin Change Interrupt Flag Register      */
00214 
00215 #define EIFR    (*(volatile unsigned char *)0x3C) /* External Interrupt Flag Register        */
00216 #define EIMSK   (*(volatile unsigned char *)0x3D) /* External Interrupt Mask Register        */
00217 
00218 #define GPIOR0  (*(volatile unsigned char *)0x3E) /* General Purpose Register 0              */
00219 
00220 #define EECR    (*(volatile unsigned char *)0x3F) /* EEPROM Control Register                 */
00221 #define EEDR    (*(volatile unsigned char *)0x40) /* EEPROM Data Register                    */
00222 #define EEAR    (*(volatile unsigned int  *)0x41) /* EEPROM Address Register                 */
00223 
00224 #define GTCCR   (*(volatile unsigned char *)0x43) /* General Purpose Register                */
00225 
00226 #define TCCR0A  (*(volatile unsigned char *)0x44) /* Timer/Counter 0 Control Register        */
00227 #define TCCR0B  (*(volatile unsigned char *)0x45) /* Timer/Counter 0 Control Register        */
00228 #define TCNT0   (*(volatile unsigned char *)0x46) /* Timer/Counter 0                         */
00229 #define OCR0A   (*(volatile unsigned char *)0x47) /* Timer/Counter 0 Output Compare Register */
00230 #define OCR0B   (*(volatile unsigned char *)0x48) /* Timer/Counter 0 Output Compare Register */
00231 
00232 #define PLLCSR  (*(volatile unsigned char *)0x49) /* PLL Control and Status Register         */
00233 
00234 #define GPIOR1  (*(volatile unsigned char *)0x4A) /* General Purpose Register 1              */
00235 #define GPIOR2  (*(volatile unsigned char *)0x4B) /* General Purpose Register 2              */
00236 
00237 #define SPCR    (*(volatile unsigned char *)0x4C) /* SPI Control Register                    */
00238 #define SPSR    (*(volatile unsigned char *)0x4D) /* SPI Status Register                     */
00239 #define SPDR    (*(volatile unsigned char *)0x4E) /* SPI I/O Data Register                   */
00240 
00241 #define ACSR    (*(volatile unsigned char *)0x50) /* Analog Comparator Control and Status Register */
00242 
00243 #define DWDR    (*(volatile unsigned char *)0x51) /* DebugWire Register                      */
00244 
00245 #define SMCR    (*(volatile unsigned char *)0x53) /* Sleep Mode Control Register             */
00246 #define MCUSR   (*(volatile unsigned char *)0x54) /* MCU Status Register                     */
00247 #define MCUCR   (*(volatile unsigned char *)0x55) /* MCU Control Register                    */
00248 
00249 #define SPMCSR  (*(volatile unsigned char *)0x57) /* Store Program Memory Control and Status Register */
00250 
00251 #define SP      (*(volatile unsigned int  *)0x5D) /* Stack Pointer                           */
00252 #define SREG    (*(volatile unsigned char *)0x5F) /* Status Register                         */
00253 
00254 #define WDTCR   (*(volatile unsigned char *)0x60) /* Watchdog Timer Control Register         */
00255 #define CLKPR   (*(volatile unsigned char *)0x61) /* Clock Prescale Register                 */
00256 #define OSCCAL  (*(volatile unsigned char *)0x66) /* Oscillator Calibration Register         */
00257 
00258 
00259 #define PCICR   (*(volatile unsigned char *)0x68) /* Pin Change interrupt enable             */
00260 
00261 #define EICRA   (*(volatile unsigned char *)0x69) /* External Interrupt Control Register A   */
00262 #define EICRB   (*(volatile unsigned char *)0x6A) /* External Interrupt Control Register B   */
00263 
00264 #define PCMSK0  (*(volatile unsigned char *)0x6B) /* Pin Change interrupt mask               */
00265 #define PCMSK1  (*(volatile unsigned char *)0x6C) /* Pin Change interrupt mask               */
00266 
00267 #define TIMSK0  (*(volatile unsigned char *)0x6E) /* Timer/Counter 0 Interrupt Mask Register */
00268 #define TIMSK1  (*(volatile unsigned char *)0x6F) /* Timer/Counter 1 Interrupt Mask Register */
00269 
00270 #define TCCR1A  (*(volatile unsigned char *)0x80) /* Timer/Counter 1 Control Register A      */
00271 #define TCCR1B  (*(volatile unsigned char *)0x81) /* Timer/Counter 1 Control Register B      */
00272 #define TCCR1C  (*(volatile unsigned char *)0x82) /* Timer/Counter 1 Control Register C      */
00273 #define TCNT1   (*(volatile unsigned int  *)0x84) /* Timer/Counter 1 Register                */
00274 #define ICR1    (*(volatile unsigned int  *)0x86) /* Timer/Counter 1 Input Capture Register  */
00275 #define OCR1A   (*(volatile unsigned int  *)0x88) /* Timer/Counter 1 Output Compare Register A */
00276 #define OCR1B   (*(volatile unsigned int  *)0x8A) /* Timer/Counter 1 Output Compare Register B */
00277 #define OCR1C   (*(volatile unsigned int  *)0x8C) /* Timer/Counter 1 Output Compare Register C */
00278 
00279 #define UCSR1A  (*(volatile unsigned char *)0xC8) /* USART1 Control and Status Register A    */
00280 #define UCSR1B  (*(volatile unsigned char *)0xC9) /* USART1 Control and Status Register B    */
00281 #define UCSR1C  (*(volatile unsigned char *)0xCA) /* USART1 Control and Status Register C    */
00282 #define UBRR1   (*(volatile unsigned int  *)0xCC) /* USART1 Baud Rate Register               */
00283 #define UBRR1L  (*(volatile unsigned char *)0xCC) /* USART1 Baud Rate Register Low           */
00284 #define UBRR1H  (*(volatile unsigned char *)0xCD) /* USART1 Baud Rate Register High          */
00285 #define UDR1    (*(volatile unsigned char *)0xCE) /* USART1 I/O Data Register                */
00286 
00287 // USB CONTROLLER
00288 // USB General
00289 // Page 1
00290 #define USBCON  (*(volatile unsigned char *)0xD8) /*   */
00291 #define UDPADDL (*(volatile unsigned char *)0xDB) /*   */
00292 #define UDPADDH (*(volatile unsigned char *)0xDC) /*   */
00293 
00294 // USB Device
00295 // Page 1
00296 #define UDCON   (*(volatile unsigned char *)0xE0) /*   */
00297 #define UDINT   (*(volatile unsigned char *)0xE1) /*   */
00298 #define UDIEN   (*(volatile unsigned char *)0xE2) /*   */
00299 #define UDADDR  (*(volatile unsigned char *)0xE3) /*   */
00300 #define UDFNUML (*(volatile unsigned char *)0xE4) /*   */
00301 #define UDFNUMH (*(volatile unsigned char *)0xE5) /*   */
00302 #define UDMFN   (*(volatile unsigned char *)0xE6) /*   */
00303 #define UDTST   (*(volatile unsigned char *)0xE7) /*   */
00304 
00305 // USB Endpoint
00306 // Page 1
00307 #define UENUM   (*(volatile unsigned char *)0xE9) /*   */
00308 #define UERST   (*(volatile unsigned char *)0xEA) /*   */
00309 #define UECONX  (*(volatile unsigned char *)0xEB) /*   */
00310 #define UECFG0X (*(volatile unsigned char *)0xEC) /*   */
00311 #define UECFG1X (*(volatile unsigned char *)0xED) /*   */
00312 #define UESTA0X (*(volatile unsigned char *)0xEE) /*   */
00313 #define UESTA1X (*(volatile unsigned char *)0xEF) /*   */
00314 #define UEINTX  (*(volatile unsigned char *)0xE8) /*   */
00315 #define UEIENX  (*(volatile unsigned char *)0xF0) /*   */
00316 #define UEDATX  (*(volatile unsigned char *)0xF1) /*   */
00317 #define UEBCLX  (*(volatile unsigned char *)0xF2) /*   */
00318 #define UEINT   (*(volatile unsigned char *)0xF4) /*   */
00319 
00320 // PS2 and USB
00321 #define PS2CON  (*(volatile unsigned char *)0xFA) /*   */
00322 #define UPOE    (*(volatile unsigned char *)0xFB) /*   */
00323 
00324 // Clock Switching
00325 #define CKSEL0  (*(volatile unsigned char *)0xD0) /*   */
00326 #define CKSEL1  (*(volatile unsigned char *)0xD1) /*   */
00327 #define CKSTA   (*(volatile unsigned char *)0xD2) /*   */
00328 
00329 
00330 /*==============================*/
00331 /* Interrupt Vector Definitions */
00332 /*==============================*/
00333 /* NB! vectors are specified as byte addresses */
00334 #define    RESET_vect           1
00335 #define    INT0_vect            2
00336 #define    INT1_vect            3
00337 #define    INT2_vect            4
00338 #define    INT3_vect            5
00339 #define    INT4_vect            6
00340 #define    INT5_vect            7
00341 #define    INT6_vect            8
00342 #define    INT7_vect            9
00343 #define    PCINT0_vect          10
00344 #define    PCINT1_vect          11
00345 #define    USB_GENERAL_vect     12
00346 #define    USB_ENDPOINT_vect    13
00347 #define    WDT_vect             14
00348 #define    TIMER1_CAPT_vect     15
00349 #define    TIMER1_COMPA_vect    16
00350 #define    TIMER1_COMPB_vect    17
00351 #define    TIMER1_COMPC_vect    18
00352 #define    TIMER1_OVF_vect 19                
00353 #define    TIMER0_COMPA_vect    20     
00354 #define    TIMER0_COMPB_vect    21
00355 #define    TIMER0_OVF_vect      22
00356 #define    SPI_STC_vect         23
00357 #define    USART1_RXC_vect      24
00358 #define    USART1_UDRE_vect     25
00359 #define    USART1_TXC_vect      26
00360 #define    ANA_COMP_vect        27
00361 #define    EE_RDY_vect          28
00362 #define    SPM_RDY_vect         29
00363 
00364 #endif /* _ICC_*/
00365 
00366 
00367 
00368 /*==========================*/
00369 /* Bit Position Definitions */
00370 /*==========================*/
00371 /* PINB : Input Pins, Port B */
00372 #define    PINB7    7
00373 #define    PINB6    6
00374 #define    PINB5    5
00375 #define    PINB4    4
00376 #define    PINB3    3
00377 #define    PINB2    2
00378 #define    PINB1    1
00379 #define    PINB0    0
00380 
00381 /* DDRB : Data Direction Register, Port B */
00382 #define    DDB7     7
00383 #define    DDB6     6
00384 #define    DDB5     5
00385 #define    DDB4     4
00386 #define    DDB3     3
00387 #define    DDB2     2
00388 #define    DDB1     1
00389 #define    DDB0     0
00390 
00391 /* PORTB : Data Register, Port B */
00392 #define    PB7      7
00393 #define    PB6      6
00394 #define    PB5      5
00395 #define    PB4      4
00396 #define    PB3      3
00397 #define    PB2      2
00398 #define    PB1      1
00399 #define    PB0      0
00400 
00401 /* PORTB : Data Register, Port B */
00402 #define    PORTB7   7
00403 #define    PORTB6   6
00404 #define    PORTB5   5
00405 #define    PORTB4   4
00406 #define    PORTB3   3
00407 #define    PORTB2   2
00408 #define    PORTB1   1
00409 #define    PORTB0   0
00410 
00411 /* PINC : Input Pins, Port C */
00412 #define    PINC7    7
00413 #define    PINC6    6
00414 #define    PINC5    5
00415 #define    PINC4    4
00416 //#define    PINC3    3
00417 #define    PINC2    2
00418 #define    PINC1    1
00419 #define    PINC0    0
00420 
00421 /* DDRC : Data Direction Register, Port C */
00422 #define    DDC7     7
00423 #define    DDC6     6
00424 #define    DDC5     5
00425 #define    DDC4     4
00426 //#define    DDC3     3
00427 #define    DDC2     2
00428 #define    DDC1     1
00429 #define    DDC0     0
00430 
00431 /* PORTC : Data Register, Port C */
00432 #define    PC7      7
00433 #define    PC6      6
00434 #define    PC5      5
00435 #define    PC4      4
00436 //#define    PC3      3
00437 #define    PC2      2
00438 #define    PC1      1
00439 #define    PC0      0
00440 
00441 /* PORTC : Data Register, Port C */
00442 #define    PORTC7   7
00443 #define    PORTC6   6
00444 #define    PORTC5   5
00445 #define    PORTC4   4
00446 //#define    PORTC3   3
00447 #define    PORTC2   2
00448 #define    PORTC1   1
00449 #define    PORTC0   0
00450 
00451 /* PIND : Input Pins, Port D */
00452 #define    PIND7    7
00453 #define    PIND6    6
00454 #define    PIND5    5
00455 #define    PIND4    4
00456 #define    PIND3    3
00457 #define    PIND2    2
00458 #define    PIND1    1
00459 #define    PIND0    0
00460 
00461 /* DDRD : Data Direction Register, Port D */
00462 #define    DDD7     7
00463 #define    DDD6     6
00464 #define    DDD5     5
00465 #define    DDD4     4
00466 #define    DDD3     3
00467 #define    DDD2     2
00468 #define    DDD1     1
00469 #define    DDD0     0
00470 
00471 /* PORTD : Data Register, Port D */
00472 #define    PD7      7
00473 #define    PD6      6
00474 #define    PD5      5
00475 #define    PD4      4
00476 #define    PD3      3
00477 #define    PD2      2
00478 #define    PD1      1
00479 #define    PD0      0
00480 
00481 /* PORTD : Data Register, Port D */
00482 #define    PORTD7   7
00483 #define    PORTD6   6
00484 #define    PORTD5   5
00485 #define    PORTD4   4
00486 #define    PORTD3   3
00487 #define    PORTD2   2
00488 #define    PORTD1   1
00489 #define    PORTD0   0
00490 
00491 /* TFR0 : Timer/Counter Interrupt Flag Register 0 */
00492 #define    OCF0B    2
00493 #define    OCF0A    1
00494 #define    TOV0     0
00495 
00496 /* TFR1 : Timer/Counter Interrupt Flag Register 1 */
00497 #define    ICF1     5
00498 #define    OCF1C    3
00499 #define    OCF1B    2
00500 #define    OCF1A    1
00501 #define    TOV1     0
00502 
00503 /* EIFR : External Interrupt Flag Register */
00504 #define    INTF7    7
00505 #define    INTF6    6
00506 #define    INTF5    5
00507 #define    INTF4    4
00508 #define    INTF3    3
00509 #define    INTF2    2
00510 #define    INTF1    1
00511 #define    INTF0    0
00512 
00513 /* EIMSK : External Interrupt Mask Register */
00514 #define    INT7     7
00515 #define    INT6     6
00516 #define    INT5     5
00517 #define    INT4     4
00518 #define    INT3     3
00519 #define    INT2     2
00520 #define    INT1     1
00521 #define    INT0     0
00522 
00523 /* EICRA : External Interrupt Control Register A*/
00524 #define    ISC31     7
00525 #define    ISC30     6
00526 #define    ISC21     5
00527 #define    ISC20     4
00528 #define    ISC11     3
00529 #define    ISC10     2
00530 #define    ISC01     1
00531 #define    ISC00     0
00532 
00533 /* EICRB : External Interrupt Control Register B*/
00534 #define    ISC71     7
00535 #define    ISC70     6
00536 #define    ISC61     5
00537 #define    ISC60     4
00538 #define    ISC51     3
00539 #define    ISC50     2
00540 #define    ISC41     1
00541 #define    ISC40     0
00542 
00543 /* EECR : EEPROM Control Register */
00544 #define    EEPM1    5
00545 #define    EEPM0    4
00546 #define    EERIE    3
00547 #define    EEMWE    2
00548 #define    EEWE     1
00549 #define    EERE     0
00550 
00551 /* GTCCR : General Timer Control Register */
00552 #define    TSM      7
00553 #define    PSR2     1
00554 #define    PSR310   0
00555 
00556 
00557 /* TCCR0A : Timer/Counter 0 Control Register */
00558 #define    COM0A1   7
00559 #define    COM0A0   6
00560 #define    COM0B1   5
00561 #define    COM0B0   4
00562 #define    WGM01    1
00563 #define    WGM00    0
00564 
00565 /* TCCR0B : Timer/Counter 0 Control Register */
00566 #define    FOC0A    7
00567 #define    FOC0B    6
00568 #define    WGM02    3
00569 #define    CS02     2
00570 #define    CS01     1
00571 #define    CS00     0
00572 
00573 /* SPCR : SPI Control Register */
00574 #define    SPIE     7
00575 #define    SPE      6
00576 #define    DORD     5
00577 #define    MSTR     4
00578 #define    CPOL     3
00579 #define    CPHA     2
00580 #define    SPR1     1
00581 #define    SPR0     0
00582 
00583 /* SPSR : SPI Status Register */
00584 #define    SPIF     7
00585 #define    WCOL     6
00586 #define    SPI2X    0
00587 
00588 /* ACSR : Analog Comparator Control and Status Register */
00589 #define    ACD      7
00590 #define    ACBG     6
00591 #define    ACO      5
00592 #define    ACI      4
00593 #define    ACIE     3
00594 #define    ACIC     2
00595 #define    ACIS1    1
00596 #define    ACIS0    0
00597 
00598 /* DWDR : DebugWire Register */
00599 #define    DWR7     7
00600 #define    DWR6     6
00601 #define    DWR5     5
00602 #define    DWR4     4
00603 #define    DWR3     3
00604 #define    DWR2     2
00605 #define    DWR1     1
00606 #define    DWR0     0
00607 
00608 /* SMCR : Sleep Mode Control Register */
00609 #define    SM2      3
00610 #define    SM1      2
00611 #define    SM0      1
00612 #define    SE       0
00613 
00614 /* MCUSR : MCU general Status Register */
00615 #define    USBRF    5
00616 #define    DWRF     4
00617 #define    WDRF     3
00618 #define    BORF     2
00619 #define    EXTRF    1
00620 #define    PORF     0
00621 
00622 /* MCUCR : MCU general Control Register */
00623 #define    DWD      7
00624 #define    PUD      4
00625 #define    IVSEL    1
00626 #define    IVCE     0
00627 
00628 /* SPMCR : Store Program Memory Control and Status Register */
00629 #define    SPMIE    7
00630 #define    RWWSB    6
00631 #define    SIGRD    5
00632 #define    RWWSRE   4
00633 #define    BLBSET   3
00634 #define    PGWRT    2
00635 #define    PGERS    1
00636 #define    SPMEN    0
00637 
00638 /* SPH : Stack Pointer High */
00639 #define    SP15     7
00640 #define    SP14     6
00641 #define    SP13     5
00642 #define    SP12     4
00643 #define    SP11     3
00644 #define    SP10     2
00645 #define    SP9      1
00646 #define    SP8      0
00647 
00648 /* SPL : Stack Pointer Low */
00649 #define    SP7      7
00650 #define    SP6      6
00651 #define    SP5      5
00652 #define    SP4      4
00653 #define    SP3      3
00654 #define    SP2      2
00655 #define    SP1      1
00656 #define    SP0      0
00657 
00658 /* WTDCR : Watchdog Timer Control Register */
00659 #define    WDIF     7
00660 #define    WDIE     6
00661 #define    WDP3     5
00662 #define    WDCE     4
00663 #define    WDE      3
00664 #define    WDP2     2
00665 #define    WDP1     1
00666 #define    WDP0     0
00667 
00668 /* CLKPR : Source Clock Prescaler Register */
00669 #define    CKLPCE   7
00670 #define    CLKPCE   7 //for compatiblity
00671 #define    CKLPS3   3
00672 #define    CKLPS2   2
00673 #define    CKLPS1   1
00674 #define    CKLPS0   0
00675 
00676 /* TIMSK0 : Timer Interrupt Mask Register0 */
00677 #define    OCIE0B   2
00678 #define    OCIE0A   1
00679 #define    TOIE0    0
00680 
00681 /* TIMSK1 : Timer Interrupt Mask Register1 */
00682 #define    ICIE1    5
00683 #define    OCIE1C   3
00684 #define    OCIE1B   2
00685 #define    OCIE1A   1
00686 #define    TOIE1    0
00687 
00688 /* TCCR1A : Timer/Counter 1 Control Register A */
00689 #define    COM1A1   7
00690 #define    COM1A0   6
00691 #define    COM1B1   5
00692 #define    COM1B0   4
00693 #define    COM1C1   3
00694 #define    COM1C0   2
00695 #define    WGM11    1
00696 #define    WGM10    0
00697 
00698 /* TCCR1B : Timer/Counter 1 Control Register B */
00699 #define    ICNC1    7
00700 #define    ICES1    6
00701 #define    WGM13    4
00702 #define    WGM12    3
00703 #define    CS12     2
00704 #define    CS11     1
00705 #define    CS10     0
00706 
00707 /* TCCR1C : Timer/Counter 1 Control Register C */
00708 #define    FOC1A    7
00709 #define    FOC1B    6
00710 #define    FOC1C    5
00711 
00712 /* UCSR0A : USART0 Control and Status Register A */
00713 #define    RXC0     7
00714 #define    TXC0     6
00715 #define    UDRE0    5
00716 #define    FE0      4
00717 #define    DOR0     3
00718 #define    UPE0     2
00719 #define    U2X0     1
00720 #define    MPCM0    0
00721 
00722 /* UCSR1A : USART1 Control and Status Register A */
00723 #define    RXC1     7
00724 #define    TXC1     6
00725 #define    UDRE1    5
00726 #define    FE1      4
00727 #define    DOR1     3
00728 #define    UPE1     2
00729 #define    U2X1     1
00730 #define    MPCM1    0
00731 
00732 /* UCSR1B : USART1 Control and Status Register B */
00733 #define    RXCIE1   7
00734 #define    TXCIE1   6
00735 #define    UDRIE1   5
00736 #define    RXEN1    4
00737 #define    TXEN1    3
00738 #define    UCSZ12   2
00739 #define    RXB81    1
00740 #define    TXB81    0
00741 
00742 /* UCSR1C : USART1 Control and Status Register C */
00743 #define    UMSEL11  7
00744 #define    UMSEL10  6
00745 #define    UMSEL1   6  // for compatibility
00746 #define    UPM11    5
00747 #define    UPM10    4
00748 #define    USBS1    3
00749 #define    UCSZ11   2
00750 #define    UCSZ10   1
00751 #define    UCPOL1   0
00752 
00753 /* UCSR1D : USART1 Control and Status Register D */
00754 #define    CTSEN    1
00755 #define    RTSEN    0
00756 
00757 /* PCICR Pin Change Interrupt control */
00758 #define    PCIE1    1
00759 #define    PCIE0    0
00760 
00761 /* PCIFR Pin Change Interrupt flag */
00762 #define    PCIF1    1
00763 #define    PCIF0    0
00764 
00765 /* ***** USB_DEVICE ******************* */
00766 /* UDCON -  */
00767 #define    DETACH          0       //
00768 #define    RMWKUP          1       //
00769 #define    RSTCPU          2       //
00770 
00771 /* UDINT -  */
00772 #define    SUSPI           0       //
00773 //#define    MSOFI           1       //
00774 #define    SOFI            2       //
00775 #define    EORSTI          3       //
00776 #define    WAKEUPI         4       //
00777 #define    EORSMI          5       //
00778 #define    UPRSMI          6       //
00779 
00780 /* UDIEN -  */
00781 #define    SUSPE           0       //
00782 //#define    MSOFE           1       //
00783 #define    SOFE            2       //
00784 #define    EORSTE          3       //
00785 #define    WAKEUPE         4       //
00786 #define    EORSME          5       //
00787 #define    UPRSME          6       //
00788 
00789 /* UDADDR -  */
00790 #define    UDADDR0         0       //
00791 #define    UDADDR1         1       //
00792 #define    UDADDR2         2       //
00793 #define    UDADDR3         3       //
00794 #define    UDADDR4         4       //
00795 #define    UDADDR5         5       //
00796 #define    UDADDR6         6       //
00797 #define    ADDEN           7       //
00798 
00799 /* UDFNUML -  */
00800 #define    UDFNUML_0       0       //
00801 #define    UDFNUML_1       1       //
00802 #define    UDFNUML_2       2       //
00803 #define    UDFNUML_3       3       //
00804 #define    UDFNUML_4       4       //
00805 #define    UDFNUML_5       5       //
00806 #define    UDFNUML_6       6       //
00807 #define    UDFNUML_7       7       //
00808 
00809 /* UDFNUMH -  */
00810 #define    UDFNUMH_0       0       //
00811 #define    UDFNUMH_1       1       //
00812 #define    UDFNUMH_2       2       //
00813 
00814 /* UDMFN -  */
00815 #define    FNCERR          4       //
00816 
00817 /* UEINTX -  */
00818 #define    TXINI           0       //
00819 #define    STALLEDI        1       //
00820 #define    RXOUTI          2       //
00821 #define    RXSTPI          3       //
00822 #define    NAKOUTI         4       //
00823 #define    RWAL            5       //
00824 #define    NAKINI          6       //
00825 #define    FIFOCON         7       //
00826 
00827 /* UENUM -  */
00828 #define    UENUM_0         0       //
00829 #define    UENUM_1         1       //
00830 #define    UENUM_2         2       //
00831 
00832 /* UERST -  */
00833 #define    EPRST0          0       //
00834 #define    EPRST1          1       //
00835 #define    EPRST2          2       //
00836 #define    EPRST3          3       //
00837 #define    EPRST4          4       //
00838 #define    EPRST5          5       //
00839 #define    EPRST6          6       //
00840 
00841 /* UECONX -  */
00842 #define    EPEN            0       //
00843 #define    RSTDT           3       //
00844 #define    STALLRQC        4       //
00845 #define    STALLRQ         5       //
00846 
00847 /* UECFG0X -  */
00848 #define    EPDIR           0       //
00849 #define    NYETDIS         1       //
00850 #define    AUTOSW          2       //
00851 #define    ISOSW           3       //
00852 #define    EPTYPE0         6       //
00853 #define    EPTYPE1         7       //
00854 
00855 /* UECFG1X -  */
00856 #define    ALLOC           1       //
00857 #define    EPBK0           2       //
00858 #define    EPBK1           3       //
00859 #define    EPSIZE0         4       //
00860 #define    EPSIZE1         5       //
00861 #define    EPSIZE2         6       //
00862 
00863 /* UESTA0X -  */
00864 #define    NBUSYBK0        0       //
00865 #define    NBUSYBK1        1       //
00866 #define    DTSEQ0          2       //
00867 #define    DTSEQ1          3       //
00868 #define    ZLPSEEN         4       //
00869 #define    UNDERFI         5       //
00870 #define    OVERFI          6       //
00871 #define    CFGOK           7       //
00872 
00873 /* UESTA1X -  */
00874 #define    CURRBK0         0       //
00875 #define    CURRBK1         1       //
00876 #define    CTRLDIR         2       //
00877 
00878 /* UEIENX -  */
00879 #define    TXINE           0       //
00880 #define    STALLEDE        1       //
00881 #define    RXOUTE          2       //
00882 #define    RXSTPE          3       //
00883 #define    NAKOUTE         4       //
00884 #define    NAKINE          6       //
00885 #define    FLERRE          7       //
00886 
00887 /* UEDATX -  */
00888 #define    UEDATX_0        0       //
00889 #define    UEDATX_1        1       //
00890 #define    UEDATX_2        2       //
00891 #define    UEDATX_3        3       //
00892 #define    UEDATX_4        4       //
00893 #define    UEDATX_5        5       //
00894 #define    UEDATX_6        6       //
00895 #define    UEDATX_7        7       //
00896 
00897 /* UEBCLX -  */
00898 #define    UEBCLX_0        0       //
00899 #define    UEBCLX_1        1       //
00900 #define    UEBCLX_2        2       //
00901 #define    UEBCLX_3        3       //
00902 #define    UEBCLX_4        4       //
00903 #define    UEBCLX_5        5       //
00904 #define    UEBCLX_6        6       //
00905 #define    UEBCLX_7        7       //
00906 
00907 /* UEBCHX -  */
00908 #define    UEBCHX_0        0       //
00909 #define    UEBCHX_1        1       //
00910 #define    UEBCHX_2        2       //
00911 
00912 /* UEINT -  */
00913 #define    UEINT_0         0       //
00914 #define    UEINT_1         1       //
00915 #define    UEINT_2         2       //
00916 #define    UEINT_3         3       //
00917 #define    UEINT_4         4       //
00918 #define    UEINT_5         5       //
00919 #define    UEINT_6         6       //
00920 
00921 
00922 /* ***** USB_GLOBAL ******************* */
00923 
00924 /* USBCON - USB General Control Register */
00925 //#define    VBUSTE          0       //
00926 //#define    IDTE            1       //
00927 //#define    OTGPADE         4       //
00928 #define    FRZCLK          5       //
00929 //#define    HOST            6       //
00930 #define    USBE            7       //
00931 
00932 /* USBSTA -  */
00933 //#define    VBUS            0       //
00934 //#define    ID              1       //
00935 //#define    SPEED1          3       //
00936 
00937 /* USBINT -  */
00938 //#define    VBUSTI          0       //
00939 //#define    IDTI            1       //
00940 
00941 /* ***** USB PS2 ******************** */
00942 
00943 /* PS2CON - PS2 Control Register */
00944 #define    PS2EN           0
00945 
00946 /* UPOE - USB PS2 Output Enable Register */
00947 #define    UPWE1           7
00948 #define    UPWE0           6
00949 #define    UPDRV1          5
00950 #define    UPDRV0          4
00951 #define    SCKI            3
00952 #define    DATAI           2
00953 #define    DPI             1
00954 #define    DMI             0
00955 
00956 
00957 /* ***** Clock Switching ************ */
00958 
00959 /* CKSEL0 - Clock Selection Register 0 */
00960 #define    RCSUT1          7
00961 #define    RCSUT0          6
00962 #define    EXSUT1          5
00963 #define    EXSUT0          4
00964 #define    RCE             3
00965 #define    EXTE            2
00966 #define    CLKS            0
00967 
00968 /* CKSEL1 - Clock Selection Register 1 */
00969 #define    RCCKSEL3        7
00970 #define    RCCKSEL2        6
00971 #define    RCCKSEL1        5
00972 #define    RCCKSEL0        4
00973 #define    EXCKSEL3        3
00974 #define    EXCKSEL2        2
00975 #define    EXCKSEL1        1
00976 #define    EXCKSEL0        0
00977 
00978 /* CKSTA  - Clock Status Register */
00979 #define    RCON            1
00980 #define    EXTON           0
00981 
00982 
00983 /* ***** PLL *********************** */
00984 
00985 /* PLLCSR - PLL Control and Status Register */
00986 #define    PLLP2           4
00987 #define    PLLP1           3
00988 #define    PLLP0           2
00989 #define    PLLE            1
00990 #define    PLOCK           0
00991 
00992 
00993 /* ***** REGULATOR ***************** */
00994 
00995 /* REGCR - 3V2 Regulator Control Register */
00996 #define    REGDIS          0
00997 
00998 
00999 
01000 
01001 /* Pointer definition */
01002 #define    XL     r26
01003 #define    XH     r27
01004 #define    YL     r28
01005 #define    YH     r29
01006 #define    ZL     r30
01007 #define    ZH     r31
01008 
01009 /* PCMSK0 */
01010 #define    PCINT6          6
01011 #define    PCINT5          5
01012 #define    PCINT4          4
01013 #define    PCINT3          3
01014 #define    PCINT2          2
01015 #define    PCINT1          1
01016 #define    PCINT0          0
01017 
01018 #endif  /* _MCU_H*/
01019 
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Generated on Fri Jun 15 14:15:32 2007 for Atmel by  doxygen 1.5.1-p1